SK-AM62A-LP: AM62x: How to obtain artifacts from TIDL tool using custom tflite model

Sopheap Key

Part Number: SK-AM62A-LP
Other Parts Discussed in Thread: AM62A7

Tool/software:

Hello TI Dev,

This is a basic custom model that I built on tensorflow/keras and convert it to tflite file. The model is non-image model.

I copied tflite file to edgeai_tidl_tool directory inside ./model/public. I already provided model config in the github.com/.../model_configs.py however, I am not sure if I provide a correct model config. The model config is shown as follow.

"cl-tfl_custom_model": create_model_config(

task_type="classification",

source=dict(

model_url="",

preprocess=dict(

resize=256,

crop=224,

data_layout="NHWC",

resize_with_pad=False,

reverse_channels=False,

session=dict(

session_name="tflitert",

model_path=os.path.join(models_base_path, "test_model.tflite"),

input_mean=[127.5, 127.5, 127.5],

input_scale=[1 / 127.5, 1 / 127.5, 1 / 127.5],

input_optimization=True,

extra_info=dict(num_images=numImages, num_classes=1001),

I have also updated the tfl_delegate.py with the following.

Here is the input and output detail from tflite model. May I ask if I set the input_mean and input_scale correctly?

Regards,

Key

4 months ago

0 Reese Grimsley 4 months ago

TI__Genius 15616 points

Hi Key,

I think the files you uploaded are broken, somehow. Could you try to reattach those?

In general for non-vision models, it will require you write some code for the preprocessing and postprocessing. The model_configs and the data pre/post processing is built for vision models.

The mean/scale is assuming that you have a 3-D (channels, height, width (CHW)) input with 3 channels, where the mean and scale are values to be applied to each value (pixel) in H, W dimensions.

What does the input/output for your model look like?

For non-image models, you may find the jupyter notebooks (which come with a disclaimer below) simpler. These carry less code/baggage compared to the osrt_python/tfl files -- that baggage is very useful for image-based models... not so much for other types.

https://github.com/TexasInstruments/edgeai-tidl-tools/blob/master/examples/jupyter_notebooks/custom-model-tfl.ipynb for TFLite models
- you will need to write a preprocess function, provide some of your own calibration data, and (optional) write a postprocessing function for the later cells that run inference with those artifacts
Disclaimer: I find jupyter in general can be unstable on longer-running cells, causing the kernel to crash. I sometimes see this for our tools (during compilation) as well as non-TI notebooks in the past (which had high resource usage/run time). If this is the case, I'd suggest extracting the code into a standalone python script

BR,
Reese

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I was able to build and perform inference of my custom model on x86 PC. Is there any guide where I can learn how to do inference on target devices? As I am aware of this, model artifacts are required to run the deployment on target devices.

Regards,
Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hello,

Please refer to the documentation linked below for running on the target device. As you say, you need the model-artifacts resulting from compilation on PC.

And for end-to-end applications, refer within the Edge AI SDK docs:

https://software-dl.ti.com/processor-sdk-linux/esd/AM62AX/latest/exports/edgeai-docs/common/sample_apps.html

BR,
Reese

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

Does it mean I need to clone EDGEAI TIDL Tool to the EVM board and run an inference just like I did it on PC?

Regards,
Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Yes. You should clone the repo on the target, but there is no need to run the setup scripts. Our SDK running on the EVM already has all dependencies installed. You may need to source the setup_env.sh script on the EVM.

From the PC, you will need to transfer the models/ and model-artifacts/ directory to your EVM into the newly cloned edgeai-tidl-tools

The same inference script on PC shall be used on the EVM.

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I want to ask and clarify on generating model artifacts. Below figure is artifacts I generated from my custom compilation and inference script on PC. Is it correct?

On EVM SDK, the directory of tidl_tools is not found when I run setup_env.sh.

Inference worked fine when I run the inference scripts; but there were several error indication. Is that okay?

Regards,
Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hello Key,

The model artifacts (from a folder structure) look okay. You're model has been parsed to create a subgraph named '3'

I am concerned though when I see the message that '1 of 1 nodes' are delegated to TIDL. Is your network only 1 layer? I expect not, so potentially a compilation error.

The errors in inference are a concern, yes. Try the following setting, and then rerun your inference (suggested to reboot first, in case there the previous error had a lasting side effect):

export TIDL_RT_DEBUG=1
/opt/vx_app_arm_remote_log.out & # run this in background
Set debug_level=2 in examples/osrt_python/common_utils.py to have more verbose output and see additional messages through the logging utility above

I think I was wrong about the setup_env.sh -- this is for PC in a new terminal environment. My apologies for the wrong suggestion. I believe you only need to set the SO=am62a environment variable.

BR,
Reese

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

This custom model consists of 1 layer (Conv2D) as I want to test whether it is working or not.

I could not obtain the vx_app_arm_remote_log.out. I set up the tidl tools on WSL and at home directory. I already set debug_level=2 in my custom compile and inference file. I uploaded log file after I followed your suggested setting (export TIDL_RT_DEBUG=1 and debug_level=2).

Fullscreen inference_log.log Download

 ****** In DelegatePrepare ****** 

 Number of subgraphs:1 , 1 nodes delegated out of 1 nodes 
 

 ****** In tidlDelegate::Init ****** 
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.3s:  VX_ZONE_ERROR:Enabled
 0.3s:  VX_ZONE_WARNING:Enabled
 0.4517s:  VX_ZONE_INIT:[tivxInit:190] Initialization Done !!!

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.27   , 0x00000000
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x00000000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x00000000
3           , DDR Cacheable       , Scratch     ,  128, 224.00  , 0x00000000
4           , DDR Cacheable       , Scratch     ,  128, 1024.00 , 0x00000000
5           , DDR Cacheable       , Persistent  ,  128, 256.40  , 0x00000000
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0x00000000
7           , DDR Cacheable       , Scratch     ,  128, 2.50    , 0x00000000
8           , DDR Cacheable       , Scratch     ,  128, 0.75    , 0x00000000
9           , DDR Cacheable       , Scratch     ,  128, 5.25    , 0x00000000
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0x00000000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
13          , DDR Cacheable       , Persistent  ,  128, 1245.57 , 0x00000000
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x00000000
15          , DDR Cacheable       , Persistent  ,  128, 0.38    , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 3563.23 
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
TIDL init call from ivision API 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.27   , 0xe92bb000
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0xe92c6000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0xe92b7000
3           , DDR Cacheable       , Scratch     ,  128, 224.00  , 0xa18bd000
4           , DDR Cacheable       , Scratch     ,  128, 1024.00 , 0xa17bd000
5           , DDR Cacheable       , Persistent  ,  128, 256.40  , 0xa177c000
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0xe92c5000
7           , DDR Cacheable       , Scratch     ,  128, 2.50    , 0xe9195000
8           , DDR Cacheable       , Scratch     ,  128, 0.75    , 0xe9194000
9           , DDR Cacheable       , Scratch     ,  128, 5.25    , 0xe9192000
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0xa173c000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0xa16bb000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0xe9191000
13          , DDR Cacheable       , Persistent  ,  128, 1245.57 , 0xa1583000
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0xe9190000
15          , DDR Cacheable       , Persistent  ,  128, 0.38    , 0xe918f000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 3563.23 
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Alg Init for Layer # -    1
PREEMPTION: Adding a new priority object for targetPriority = 0, handle = 0x7f3ae92bb000
PREEMPTION: Now total number of priority objects = 1 at priorityId = 0,    with new memRec of base = 0x7f3ae9191000 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x7f3ae92bb000, return Addr = 0x7f3aaed007b8
************ TIDL_subgraphRtCreate done ************ 
 
 ****** tidlDelegate::Prepare ****** 
 Outputs Tensor name and id -  StatefulPartitionedCall_1:0, 3

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
TIDL_activate is called with handle : 0x7f3ae92bb000 - Copying handle of size 19736 from 0x7f3ae92bb000 to 0x7f3aa18af000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 255.000000 930.000000 509.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 2.000000 86.000000 89.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 86.000000 37.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 84.000000 34.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 75.000000 42.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 82.000000 34.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 68.000000 42.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 93.000000 35.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 76.000000 32.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 67.000000 41.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 84.000000 34.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 74.000000 31.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 73.000000 31.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 52.000000 193.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 307.000000 31.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 79.000000 30.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 63.000000 29.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 59.000000 43.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 81.000000 35.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ****** tidlDelegate::Invoke ****** 
*******   In TIDL_subgraphRtInvoke  ******** 
TIDL_process is started with handle : 0time invoked: 0.0017s
time invoked: 0.0002s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0003s
time invoked: 0.0003s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
time invoked: 0.0001s
Output:
[[[[-0.01965912  0.03931824]
   [-0.19003816 -0.12450776]
   [-0.21625032 -0.17693208]
   [ 0.12450776  0.17037904]
   [-0.10484864 -0.09174256]]

  [[-0.08518952 -0.07863648]
   [ 0.23590943  0.15071991]
   [ 0.20314424  0.1310608 ]
   [-0.327652   -0.35386416]
   [ 0.15071991  0.07208344]]

  [[-0.01310608  0.05242432]
   [-0.2948868  -0.23590943]
   [-0.17693208 -0.18348512]
   [ 0.33420503  0.30799288]
   [-0.163826   -0.13761383]]

  [[-0.28178072  0.07863648]
   [ 0.03931824  0.3473111 ]
   [ 0.0327652   0.1965912 ]
   [-0.49803102 -0.22280335]
   [-0.00655304  0.1965912 ]]

  [[-0.40628847 -0.27522767]
   [-0.62909186 -0.3931824 ]
   [-0.38662934 -0.11795472]
   [-0.13761383  0.        ]
   [-0.4259476  -0.17693208]]]]
x7f3ae92bb000 
Core 0 Alg Process for Layer # -    1, layer type 1
Processing Layer # -    1
Core 0 End of Layer # -    1 with outPtrs[0] = 0x7f3ae92c8000
TIDL_process is completed with handle : 0x7f3ae92bb000 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 1.000000 91.000000 37.000000 
*******  TIDL_subgraphRtInvoke done  ******** 
************ in ~tidlDelegate ************ 
 ************ in TIDL_subgraphRtDelete ************ 
 TIDL_deactivate is called with handle : 0x7f3ae92bb000 - Copying handle of size 19736 from 0x7f3aa18af000 to 0x7f3ae92bb000 
MEM: Deinit ... !!!
MEM: Alloc's: 26 alloc's of 5413731 bytes 
MEM: Free's : 26 free's  of 5413731 bytes 
MEM: Open's : 0 allocs  of 0 bytes 
MEM: Deinit ... Done !!!

Regards,

Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Got it, single layer network for testing. That makes sense -- just needed to be sure this was expected and not the result of a model parsing error.

This looks like you ran on WSL / PC here, correct? The logs look correct here -- I see no issues.

But it seems that you have a different experience on the EVM. Could you produce logs with the same configuration on the EVM for your model?

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

This is the log file from inference on EVM.

It worked well. Is there anything you notice in the log file?

Fullscreen 8306.output.log Download

****** In DelegatePrepare ******

 Number of subgraphs:1 , 1 nodes delegated out of 1 nodes


 ****** In tidlDelegate::Init ******
************ in TIDL_subgraphRtCreate ************
 APP: Init ... !!!
   823.841799 s: MEM: Init ... !!!
   823.841855 s: MEM: Initialized DMA HEAP (fd=6) !!!
   823.842015 s: MEM: Init ... Done !!!
   823.842039 s: IPC: Init ... !!!
   823.858669 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
   823.862510 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
   823.862651 s:  VX_ZONE_INIT:Enabled
   823.862667 s:  VX_ZONE_ERROR:Enabled
   823.862676 s:  VX_ZONE_WARNING:Enabled
   823.863634 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-0
   823.863899 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-1
   823.864127 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-2
   823.864400 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-3
   823.864440 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
   823.864968 s:  VX_ZONE_INIT:[tivxHostInitLocal:106] Initialization Done for HOST !!!
   823.871406 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   823.871447 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   823.871459 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   823.871471 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   823.871486 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   823.871519 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   823.871530 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
TIDL_RT_OVX: ERROR: Verifying TIDL graph ... Failed !!!
TIDL_RT_OVX: ERROR: Verify OpenVX graph failed
RT-Profile: TIDLRT_init_profiling
tidlrt_create            :       32224380 ns,
tidl_rt_ovx_Init         :       25285175 ns,
vxCreateContext          :        1347945 ns,
init_tidl_tiovx          :        3232945 ns,
create_graph_tidl_tiovx  :         443765 ns,
verify_graph_tidl_tiovx  :        1661990 ns,
tivxTIDLLoadKernels      :          43275 ns,
mapConfig                :         596290 ns,
tivxAddKernelTIDL        :         119370 ns,
mapNetwork               :        1853110 ns,
setCreateParams          :         220655 ns,
setArgs                  :         395970 ns,
vxCreateUserDataObject   :          41710 ns,
vxMapUserDataObject      :         986260 ns,
memcopy_network_buffer   :         724935 ns,
vxUnmapUserDataObject    :          96890 ns,
************ TIDL_subgraphRtCreate done ************

 ****** tidlDelegate::Prepare ******
 Outputs Tensor name and id -  StatefulPartitionedCall_1:0, 3

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   823.875214 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   823.875243 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   823.875255 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   823.875266 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   823.875281 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   823.875297 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   823.875307 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   823.875409 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   823.875421 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   823.875431 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 104.000000 2074.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0023s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   823.877106 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   823.877127 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.209241 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.209264 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.209280 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.209304 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.209314 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.209429 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.209441 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.209451 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 43.000000 333427.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3336s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.211095 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.211119 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.211130 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.211141 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.211155 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.211171 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.211181 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.211282 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.211293 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.211303 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 49.000000 1352.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0015s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.212780 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.212798 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.212809 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.212820 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.212833 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.212849 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.212859 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.212955 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.212966 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.212976 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 40.000000 1256.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.543435 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.543454 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.543466 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.543476 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.543489 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.543505 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.543515 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.543641 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.543654 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.543664 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 41.000000 1276.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3305s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.545059 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.545076 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.545087 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.545098 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.545112 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.545127 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.545138 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.545235 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.545246 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.545256 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 35.000000 1245.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.546572 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.546589 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.546600 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.546611 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.546624 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.546639 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.546649 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.546745 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.546756 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.546766 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 31.000000 1229.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3301s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.877101 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.877122 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.877134 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.877145 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.877160 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.877176 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.877187 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.877288 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.877299 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.877309 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 53.000000 1331.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0015s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.878693 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.878712 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.878723 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.878734 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.878747 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.878762 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.878773 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.878870 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   824.878881 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   824.878891 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 1247.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   824.880223 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   824.880241 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   824.880252 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   824.880263 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   824.880276 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   824.880291 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   824.880301 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   824.880397 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.208601 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.208613 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 32.000000 329435.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3296s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.210013 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.210030 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.210042 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.210053 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.210066 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.210080 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.210091 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.210188 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.210200 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.210210 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 38.000000 1266.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.211538 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.211592 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.211604 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.211615 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.211629 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.211643 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.211654 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.211753 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.211764 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.211774 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 34.000000 1259.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.213146 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.213164 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.213176 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.213186 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.213200 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.213215 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.541740 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.541850 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.541863 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.541873 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 329784.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3299s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.543356 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.543375 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.543387 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.543398 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.543411 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.543427 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.543437 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.543535 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.543547 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.543593 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 43.000000 1326.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0015s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.544982 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.545000 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.545011 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.545022 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.545035 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.545050 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.545061 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.545157 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.545169 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.545179 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 37.000000 1257.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.546482 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.546498 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.546510 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.546521 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.874896 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.874931 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.874942 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.875055 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.875068 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.875077 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 32.000000 329614.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3298s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.876729 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.876752 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.876764 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.876775 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.876789 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.876805 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.876816 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.876916 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.876927 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.876937 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 110.000000 1304.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0015s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.878343 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.878362 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.878373 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   825.878385 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   825.878398 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   825.878413 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   825.878423 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   825.878520 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   825.878531 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   825.878541 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 35.000000 1249.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   825.879885 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   825.879903 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   825.879915 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   826.207986 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   826.208000 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   826.208016 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   826.208026 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   826.208126 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   826.208138 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   826.208148 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 33.000000 329319.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.3295s

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
   826.209554 s:  VX_ZONE_ERROR:[ownContextSendCmd:885] Command ack message returned failure cmd_status: -1
   826.209573 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
   826.209584 s:  VX_ZONE_ERROR:[ownNodeKernelInit:593] Please be sure the target callbacks have been registered for this core
   826.209595 s:  VX_ZONE_ERROR:[ownNodeKernelInit:594] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
   826.209609 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:620] kernel init for node 0, kernel com.ti.tidl:1:1 ... failed !!!
   826.209624 s:  VX_ZONE_ERROR:[vxVerifyGraph:2254] Node kernel init failed
   826.209634 s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
   826.209731 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:919] graph is not in a state required to be scheduled
   826.209742 s:  VX_ZONE_ERROR:[vxProcessGraph:844] schedule graph failed
   826.209752 s:  VX_ZONE_ERROR:[vxProcessGraph:849] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 37.000000 1254.000000 145515957149435.000000
*******  TIDL_subgraphRtInvoke done  ********
time invoked: 0.0014s
Output:
[[[[ 0.0000000e+00  0.0000000e+00]
   [ 4.4981681e-43  0.0000000e+00]
   [ 9.2964068e-37  0.0000000e+00]
   [-3.6677120e-12  9.1834095e-41]
   [ 0.0000000e+00  0.0000000e+00]]

  [[ 0.0000000e+00  1.3544721e-14]
   [ 0.0000000e+00  0.0000000e+00]
   [ 1.7852952e-37  1.7920781e+04]
   [ 1.2098422e-23  0.0000000e+00]
   [ 0.0000000e+00  0.0000000e+00]]

  [[ 0.0000000e+00  1.9413374e-31]
   [ 1.0910510e-41  0.0000000e+00]
   [ 0.0000000e+00  0.0000000e+00]
   [ 0.0000000e+00  5.9835444e-43]
   [ 0.0000000e+00  5.2897251e-38]]

  [[ 4.0305267e-40  3.0969893e-21]
   [ 0.0000000e+00  0.0000000e+00]
   [ 0.0000000e+00  0.0000000e+00]
   [ 2.9622458e-36  1.5574031e-41]
   [ 0.0000000e+00  0.0000000e+00]]

  [[ 0.0000000e+00  0.0000000e+00]
   [ 2.3962204e-43  0.0000000e+00]
   [ 6.2827923e-38  0.0000000e+00]
   [ 7.6223462e-39  1.8797117e-31]
   [ 0.0000000e+00  0.0000000e+00]]]]
************ in ~tidlDelegate ************
 ************ in TIDL_subgraphRtDelete ************
    826.255547 s:  VX_ZONE_INIT:[tivxHostDeInitLocal:120] De-Initialization Done for HOST !!!
   826.260136 s:  VX_ZONE_INIT:[tivxDeInitLocal:206] De-Initialization Done !!!
APP: Deinit ... !!!
REMOTE_SERVICE: Deinit ... !!!
REMOTE_SERVICE: Deinit ... Done !!!
   826.260591 s: IPC: Deinit ... !!!
   826.261058 s: IPC: DeInit ... Done !!!
   826.261103 s: MEM: Deinit ... !!!
   826.261118 s: DDR_SHARED_MEM: Alloc's: 8 alloc's of 2881304 bytes
   826.261129 s: DDR_SHARED_MEM: Free's : 8 free's  of 2881304 bytes
   826.261139 s: DDR_SHARED_MEM: Open's : 0 allocs  of 0 bytes
   826.261154 s: MEM: Deinit ... Done !!!
APP: Deinit ... Done !!!

Regards,

Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

This log certainly contains errors -- the model failed to initialize properly. It looks like inference still ran here, and the TIDL stack continued to show similar TIOVX / VX_ZONE_ERROR messages indicating the model did not actually run. I suspect the final output data is effectively garbage.

So we are seeing that the same model-artifacts are working correctly on PC with TIDL-emulation, but failing to initialize on the target. The logs do not indicate memory-related issue, which is a common source of difference between inference w/ PC-side emulation vs. on-target.

So we need to determine why you see only EVM/target side failures. It may help if you provide me your model-artifacts directory and any of the scripts you are using. Please:

Reset the EVM -- do a full power cycle, please!
Run `/opt/vx_app_arm_remote_log.out &` in the background on the EVM, right after login. This is especially important when looking for target-only issues
Run your application again for this model -- just 2-3 iterations is fine.
- Run with debug_level=2 (or debug_level=5 for maximum verbosity)
- export TIDL_RT_DEBUG=1

BR,
Reese

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I have done as you suggested; however, I still saw the same message.

The message from vx_app_arm_remote_log file is in the zip file. The model artifacts, tflite model, and inference scripts are attached in the zip file. Please have a look at it and let me know your opinion.

5826.custom.zip

Regards,
Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Hmm, this runs without that error on my side. I am using the 10.1 SDK with the starter-kit EVM

Are you on the 10.1 SDK? You can check on device like so:

#  echo $EDGEAI_SDK_VERSION
10_01_00

If you were not, then I expect to have seen other error messages. Compiled model artifacts are compatible only with the SDK and device they targeted (so AM62A, 10.1 SDK)

My log shows typical output messages. I see the following when I run your example, no modifications:

root@am62axx-evm:/tmp/5826.custom/custom# python3 tflrt_inference_custom.py

 ****** In DelegatePrepare ******

 Number of subgraphs:1 , 1 nodes delegated out of 1 nodes


 ****** In tidlDelegate::Init ******
************ in TIDL_subgraphRtCreate ************
 APP: Init ... !!!
433297.067861 s: MEM: Init ... !!!
433297.067930 s: MEM: Initialized DMA HEAP (fd=6) !!!
433297.068111 s: MEM: Init ... Done !!!
433297.068139 s: IPC: Init ... !!!
433297.085681 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
433297.090269 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
433297.090428 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
433297.090457 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
433297.090468 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
433297.091806 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-0
433297.092428 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-1
433297.092775 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-2
433297.093277 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-3
433297.093559 s:  VX_ZONE_INFO: [tivxInitLocal:126] Initialization Done !!!
433297.093629 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[C7x_1 ] 433297.099874 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0
[C7x_1 ] 433297.099899 s:
[C7x_1 ] 433297.099920 s: --------------------------------------------
[C7x_1 ] 433297.099946 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 433297.099988 s: MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr
[C7x_1 ] 433297.100036 s: 0           , DDR Cacheable       , Persistent  ,  128, 19.27   , 0x00000000
[C7x_1 ] 433297.100082 s: 1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x00000000
[C7x_1 ] 433297.100127 s: 2           , L1D                 , Scratch     ,  128, 16.00   , 0x00000000
[C7x_1 ] 433297.100178 s: 3           , L2                  , Scratch     ,  128, 224.00  , 0x00000000
[C7x_1 ] 433297.100226 s: 4           , L3/MSMC             , Scratch     ,  128, 1024.00 , 0x00000000
[C7x_1 ] 433297.100272 s: 5           , DDR Cacheable       , Persistent  ,  128, 263.28  , 0x00000000
[C7x_1 ] 433297.100315 s: 6           , DDR Cacheable       , Scratch     ,  128, 0.38    , 0x00000000
[C7x_1 ] 433297.100360 s: 7           , DDR Cacheable       , Persistent  ,  128, 2.50    , 0x00000000
[C7x_1 ] 433297.100404 s: 8           , DDR Cacheable       , Scratch     ,  128, 0.13    , 0x00000000
[C7x_1 ] 433297.100446 s: 9           , DDR Cacheable       , Scratch     ,  128, 3.13    , 0x00000000
[C7x_1 ] 433297.100490 s: 10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0x00000000
[C7x_1 ] 433297.100533 s: 11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
[C7x_1 ] 433297.100576 s: 12          , DDR Cacheable       , Persistent  ,  128, 0.13    , 0x00000000
[C7x_1 ] 433297.100620 s: 13          , DDR Cacheable       , Persistent  ,  128, 1245.44 , 0x00000000
[C7x_1 ] 433297.100664 s: 14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x00000000
[C7x_1 ] 433297.100708 s: 15          , DDR Cacheable       , Persistent  ,  128, 0.38    , 0x00000000
[C7x_1 ] 433297.100738 s: --------------------------------------------
[C7x_1 ] 433297.100765 s: Total memory size requirement (space wise):
[C7x_1 ] 433297.100787 s: Mem Space , Size(KBytes)
[C7x_1 ] 433297.100810 s: L1D       , 16.00
[C7x_1 ] 433297.100832 s: L2        , 224.00
[C7x_1 ] 433297.100854 s: L3/MSMC   , 1024.00
[C7x_1 ] 433297.100878 s: DDR Cacheable, 2303.10
[C7x_1 ] 433297.100904 s: --------------------------------------------
[C7x_1 ] 433297.100939 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
[C7x_1 ] 433297.100977 s:       To get the actual TIDL memory requirement make sure to run on EVM with
[C7x_1 ] 433297.101002 s:       debugTraceLevel = 2
[C7x_1 ] 433297.101013 s:
[C7x_1 ] 433297.101034 s: --------------------------------------------
[C7x_1 ] 433297.101169 s: TIDL init call from ivision API
[C7x_1 ] 433297.101190 s:
[C7x_1 ] 433297.101208 s: --------------------------------------------
[C7x_1 ] 433297.101234 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 433297.101274 s: MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr
[C7x_1 ] 433297.101320 s: 0           , DDR Cacheable       , Persistent  ,  128, 19.27   , 0xb2875f40
[C7x_1 ] 433297.101365 s: 1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0xb287ad00
[C7x_1 ] 433297.101410 s: 2           , L1D                 , Scratch     ,  128, 16.00   , 0x7f03c000
[C7x_1 ] 433297.101455 s: 3           , L2                  , Scratch     ,  128, 224.00  , 0x7f000000
[C7x_1 ] 433297.101500 s: 4           , L3/MSMC             , Scratch     ,  128, 1024.00 , 0x7e000000
[C7x_1 ] 433297.101545 s: 5           , DDR Cacheable       , Persistent  ,  128, 263.28  , 0xb287b040
[C7x_1 ] 433297.101588 s: 6           , DDR Cacheable       , Scratch     ,  128, 0.38    , 0xb9000000
[C7x_1 ] 433297.101632 s: 7           , DDR Cacheable       , Persistent  ,  128, 2.50    , 0xb28bce00
[C7x_1 ] 433297.101676 s: 8           , DDR Cacheable       , Scratch     ,  128, 0.13    , 0xb9000400
[C7x_1 ] 433297.101719 s: 9           , DDR Cacheable       , Scratch     ,  128, 3.13    , 0xb9000800
[C7x_1 ] 433297.101764 s: 10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0xb28bd840
[C7x_1 ] 433297.101807 s: 11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0xb9001800
[C7x_1 ] 433297.101851 s: 12          , DDR Cacheable       , Persistent  ,  128, 0.13    , 0xb28fd700
[C7x_1 ] 433297.101895 s: 13          , DDR Cacheable       , Persistent  ,  128, 1245.44 , 0xb28fd7c0
[C7x_1 ] 433297.101939 s: 14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0xb2a34e00
[C7x_1 ] 433297.101983 s: 15          , DDR Cacheable       , Persistent  ,  128, 0.38    , 0xb2a34ec0
[C7x_1 ] 433297.102013 s: --------------------------------------------
[C7x_1 ] 433297.102038 s: Total memory size requirement (space wise):
[C7x_1 ] 433297.102060 s: Mem Space , Size(KBytes)
[C7x_1 ] 433297.102081 s: L1D       , 16.00
[C7x_1 ] 433297.102103 s: L2        , 224.00
[C7x_1 ] 433297.102125 s: L3/MSMC   , 1024.00
[C7x_1 ] 433297.102147 s: DDR Cacheable, 2303.10
[C7x_1 ] 433297.102179 s: --------------------------------------------
[C7x_1 ] 433297.102215 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
[C7x_1 ] 433297.102254 s:       To get the actual TIDL memory requirement make sure to run on EVM with
[C7x_1 ] 433297.102278 s:       debugTraceLevel = 2
RT-Profile: TIDLRT_init_profiling
[C7x_1 ] 433297.102289 s:
[C7x_1 ] 433297.102309 s: --------------------------------------------
tidlrt_create            :       45022944 ns,
tidl_rt_ovx_Init         :       28173013 ns,
[C7x_1 ] 433297.105931 s: Alg Init for Layer # -    1
vxCreateContext          :        1411854 ns,
init_tidl_tiovx          :        3068559 ns,
create_graph_tidl_tiovx  :         446698 ns,
verify_graph_tidl_tiovx  :       11640193 ns,
tivxTIDLLoadKernels      :          44240 ns,
[C7x_1 ] 433297.106115 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b2875f40
mapConfig                :         710854 ns,
tivxAddKernelTIDL        :         116071 ns,
mapNetwork               :        1634475 ns,
setCreateParams          :         254427 ns,
[C7x_1 ] 433297.106178 s: PREEMPTION: Now total number of priority objects = 2 at priorityId = 0,    with new memRec of base = b28fd700 and size = 128
setArgs                  :         305022 ns,
vxCreateUserDataObject   :          39780 ns,
vxMapUserDataObject      :         895891 ns,
[C7x_1 ] 433297.106239 s: PREEMPTION: Requesting context memory addr for handle b2875f40, return Addr = 9a2cfff0
memcopy_network_buffer   :         605619 ns,
vxUnmapUserDataObject    :          90440 ns,
[C7x_1 ] 433297.106272 s: Print preEmption Hnadle during init stage :
************ TIDL_subgraphRtCreate done ************
[C7x_1 ] 433297.106298 s: ProcTime,      ctxSize,       dataId
[C7x_1 ] 433297.106326 s: 0.000,         6460,            0
[C7x_1 ] 433297.106353 s: 0.009,         6460,            1
[C7x_1 ] 433297.106380 s: 0.000,            0,            2
[C7x_1 ] 433297.106412 s: TIDL_initializeHandleForPreemption is completed

 ****** tidlDelegate::Prepare ******
 Outputs Tensor name and id -  StatefulPartitionedCall_1:0, 3

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          58788,           3465,           6484,          16698,           3731,                 0,              0,                 0,              0,              0,            684,              1,              0,           5439,              0,              0,              0,
 Sum of Layer Cycles 58788
Sub Graph Stats 131.000000 1267.000000 412.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56309,           3358,           5799,          16310,           3736,                 0,              0,                 0,              0,              0,            592,              1,              0,           6026,              0,              0,              0,
 Sum of Layer Cycles 56309
Sub Graph Stats 40.000000 1022.000000 381.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56875,           3395,           5804,          16120,           3462,                 0,              0,                 0,              0,              0,            573,              1,              0,           5986,              0,              0,              0,
 Sum of Layer Cycles 56875
Sub Graph Stats 39.000000 1002.000000 279.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          52323,           2593,           5006,          13678,           3244,                 0,              0,                 0,              0,              0,            571,              1,              0,           4028,              0,              0,              0,
 Sum of Layer Cycles 52323
Sub Graph Stats 34.000000 1008.000000 251.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          55791,           3233,           5946,          16644,           3464,                 0,              0,                 0,              0,              0,            877,              1,              0,           5922,              0,              0,              0,
 Sum of Layer Cycles 55791
Sub Graph Stats 35.000000 1007.000000 281.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
[C7x_1 ] 433297.112622 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.112665 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.112710 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.112762 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.112874 s: TIDL_activate is called with handle : b2875f40 - Copying handle of size 19736 from b2875f40 to 7e0f2000
[C7x_1 ] 433297.112935 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.112977 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.113022 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.113074 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.113116 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.113145 s: Processing Layer # -    1
[C7x_1 ] 433297.113210 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.113251 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.113301 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.113347 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.113399 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.113441 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.113476 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.113516 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.114587 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.114629 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.114675 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.114726 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.114774 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.114816 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.114862 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.114914 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.114956 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.114985 s: Processing Layer # -    1
[C7x_1 ] 433297.115048 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.115087 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.115127 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.115182 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.115236 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.115276 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.115311 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.115351 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.116324 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.116367 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.116413 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.116466 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.116515 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.116557 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.116601 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.116653 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.116696 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.116725 s: Processing Layer # -    1
[C7x_1 ] 433297.116788 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.116826 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
[C7x_1 ] 433297.116866 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.116910 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
     1,          52156,           2553,           4960,          13988,           3244,                 0,              0,                 0,              0,              0,            571,              1,              0,           4312,              0,              0,              0,
 Sum of Layer Cycles 52156
[C7x_1 ] 433297.116962 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.117002 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.117036 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.117076 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.117885 s: TIDL_process is started with handle : b2875f40
Sub Graph Stats 37.000000 1063.000000 296.000000
*******  TIDL_subgraphRtInvoke done  ********
[C7x_1 ] 433297.117928 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.117975 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.118027 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.118075 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.118117 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.118174 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.118229 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.118271 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.118299 s: Processing Layer # -    1
[C7x_1 ] 433297.118359 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000

 ****** tidlDelegate::Invoke ******
[C7x_1 ] 433297.118397 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
*******   In TIDL_subgraphRtInvoke  ********
[C7x_1 ] 433297.118438 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.118483 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.118536 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.118576 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.118611 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.118652 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.119428 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.119470 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.119515 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.119566 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.119615 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.119656 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.119701 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.119753 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.119795 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.119823 s: Processing Layer # -    1
[C7x_1 ] 433297.119886 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.119925 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.119966 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.120011 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.120064 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.120103 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.120138 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.120188 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.121031 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.121074 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.121120 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.121172 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.121220 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.121273 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.121319 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.121371 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.121415 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.121443 s: Processing Layer # -    1
[C7x_1 ] 433297.121503 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.121541 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.121581 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.121625 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.121677 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.121716 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.121750 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.121791 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.122698 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.122741 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.122787 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.122839 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.122886 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.122928 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.122974 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.123025 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.123068 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.123096 s: Processing Layer # -    1
[C7x_1 ] 433297.123159 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
[C7x_1 ] 433297.123197 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.123245 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
     1,          55345,           3107,           5828,          16296,           3498,                 0,              0,                 0,              0,              0,            883,              1,              0,           6272,              0,              0,              0,
 Sum of Layer Cycles 55345
[C7x_1 ] 433297.123290 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.123341 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.123380 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.123415 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
Sub Graph Stats 35.000000 1026.000000 306.000000
[C7x_1 ] 433297.123455 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56461,           3352,           5814,          16228,           3467,                 0,              0,                 0,              0,              0,            617,              1,              0,           6062,              0,              0,              0,
 Sum of Layer Cycles 56461
Sub Graph Stats 37.000000 1018.000000 273.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          54480,           2362,           5049,          14510,           3605,                 0,              0,                 0,              0,              0,            849,              1,              0,           4662,              0,              0,              0,
 Sum of Layer Cycles 54480
Sub Graph Stats 36.000000 1010.000000 250.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56009,           3201,           5622,          16250,           3458,                 0,              0,                 0,              0,              0,            573,              1,              0,           5904,              0,              0,              0,
 Sum of Layer Cycles 56009
Sub Graph Stats 32.000000 1009.000000 341.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          52403,           2523,           4932,          13760,           3262,                 0,              0,                 0,              0,              0,            573,              1,              0,           4072,              0,              0,              0,
 Sum of Layer Cycles 52403
Sub Graph Stats 38.000000 1018.000000 259.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          57339,           3142,           5897,          16864,           3455,                 0,              0,                 0,              0,              0,            909,              1,              0,           6528,              0,              0,              0,
 Sum of Layer Cycles 57339
Sub Graph Stats 34.000000 1005.000000 293.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          55477,           3347,           5756,          16154,           3466,                 0,              0,                 0,              0,              0,            573,              1,              0,           5974,              0,              0,              0,
 Sum of Layer Cycles 55477
Sub Graph Stats 36.000000 1003.000000 261.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
[C7x_1 ] 433297.124338 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.124381 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.124427 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.124480 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.124529 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.124571 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.124615 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.124668 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.124710 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.124739 s: Processing Layer # -    1
[C7x_1 ] 433297.124802 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.124840 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.124880 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.124924 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.124976 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.125015 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.125050 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.125090 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.125916 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.125959 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.126005 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.126058 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.126106 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.126148 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.126207 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.126260 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.126303 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.126332 s: Processing Layer # -    1
[C7x_1 ] 433297.126393 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.126431 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.126470 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.126515 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.126567 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.126606 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.126640 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.126681 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.127435 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.127478 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
[C7x_1 ] 433297.127524 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
     1,          55589,           3270,           5675,          16162,           3459,                 0,              0,                 0,              0,              0,            565,              1,              0,           6014,              0,              0,              0,
[C7x_1 ] 433297.127576 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
 Sum of Layer Cycles 55589
[C7x_1 ] 433297.127626 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.127669 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.127713 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
Sub Graph Stats 32.000000 1030.000000 304.000000
[C7x_1 ] 433297.127765 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
*******  TIDL_subgraphRtInvoke done  ********
[C7x_1 ] 433297.127808 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.127836 s: Processing Layer # -    1
[C7x_1 ] 433297.127899 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.127938 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.127979 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.128023 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.128075 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.128115 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.128150 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.128197 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced

 ****** tidlDelegate::Invoke ******
[C7x_1 ] 433297.129115 s: TIDL_process is started with handle : b2875f40
*******   In TIDL_subgraphRtInvoke  ********
[C7x_1 ] 433297.129169 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.129215 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.129268 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.129316 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.129358 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.129403 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.129455 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.129499 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.129527 s: Processing Layer # -    1
[C7x_1 ] 433297.129587 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.129625 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.129667 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.129711 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.129763 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.129802 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.129837 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.129877 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.130669 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.130712 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.130758 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.130811 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.130860 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.130901 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.130946 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.130998 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.131041 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.131070 s: Processing Layer # -    1
[C7x_1 ] 433297.131134 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.131172 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.131220 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.131266 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.131319 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.131358 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.131393 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.131432 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.132282 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.132325 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.132371 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.132423 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.132471 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.132513 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.132558 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.132609 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.132651 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.132680 s: Processing Layer # -    1
[C7x_1 ] 433297.132743 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.132782 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.132823 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.132868 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.132921 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.132960 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.132995 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.133036 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.133813 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.133856 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.133902 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.133955 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.134004 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.134046 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.134091 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.134143 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.134186 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.134214 s: Processing Layer # -    1
[C7x_1 ] 433297.134277 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
[C7x_1 ] 433297.134316 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.134363 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
     1,          55276,           3139,           5620,          16096,           3452,                 0,              0,                 0,              0,              0,            645,              1,              0,           6098,              0,              0,              0,
 Sum of Layer Cycles 55276
[C7x_1 ] 433297.134408 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.134460 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.134499 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.134534 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
Sub Graph Stats 35.000000 1034.000000 587.000000
[C7x_1 ] 433297.134574 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
*******  TIDL_subgraphRtInvoke done  ********
[C7x_1 ] 433297.135466 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.135509 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.135555 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.135608 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.135657 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.135699 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.135745 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.135797 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.135840 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.135869 s: Processing Layer # -    1
[C7x_1 ] 433297.135932 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
[C7x_1 ] 433297.135971 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.136011 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.136055 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.136108 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.136147 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.136182 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.136230 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          57413,           3347,           5756,          16126,           3452,                 0,              0,                 0,              0,              0,            573,              1,              0,           5930,              0,              0,              0,
 Sum of Layer Cycles 57413
Sub Graph Stats 38.000000 1028.000000 263.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          52003,           2535,           4995,          13754,           3260,                 0,              0,                 0,              0,              0,            618,              1,              0,           4078,              0,              0,              0,
 Sum of Layer Cycles 52003
Sub Graph Stats 28.000000 1003.000000 246.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          57798,           3363,           6014,          16604,           3454,                 0,              0,                 0,              0,              0,            815,              1,              0,           5832,              0,              0,              0,
 Sum of Layer Cycles 57798
Sub Graph Stats 29.000000 996.000000 490.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56346,           3173,           5842,          16690,           3462,                 0,              0,                 0,              0,              0,            833,              1,              0,           6330,              0,              0,              0,
 Sum of Layer Cycles 56346
Sub Graph Stats 32.000000 1014.000000 249.000000
*******  TIDL_subgraphRtInvoke done  ********

 ****** tidlDelegate::Invoke ******
*******   In TIDL_subgraphRtInvoke  ********
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,          56287,           3466,           5884,          16034,           3454,                 0,              0,                 0,              0,              0,            573,              1,              0,           6030,              0,              0,              0,
 Sum of Layer Cycles 56287
Sub Graph Stats 29.000000 1001.000000 245.000000
*******  TIDL_subgraphRtInvoke done  ********
[C7x_1 ] 433297.137429 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.137471 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.137517 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.137569 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.137617 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.137659 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.137704 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.137754 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.137796 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.137826 s: Processing Layer # -    1
[C7x_1 ] 433297.137889 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.137928 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.137970 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.138015 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.138067 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.138107 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.138141 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.138188 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.138964 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.139007 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.139053 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.139106 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.139155 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.139207 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.139252 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.139305 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.139349 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.139377 s: Processing Layer # -    1
[C7x_1 ] 433297.139436 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.139475 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.139515 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.139559 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.139612 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.139651 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.139685 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.139725 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.140456 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.140499 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.140545 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.140597 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.140645 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.140687 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.140732 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.140784 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.140827 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.140857 s: Processing Layer # -    1
[C7x_1 ] 433297.140921 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.140959 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.141000 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.141044 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.141096 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.141135 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.141170 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.141217 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.142237 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.142280 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.142326 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.142378 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.142427 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.142470 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.142515 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.142566 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.142610 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.142638 s: Processing Layer # -    1
[C7x_1 ] 433297.142702 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.142741 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.142782 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.142827 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.142879 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.142918 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.142953 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.142993 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.143726 s: TIDL_process is started with handle : b2875f40
[C7x_1 ] 433297.143769 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.143815 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.143867 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[[[[-0.25556856 -0.15071991]
   [ 0.0655304   0.12450776]
   [ 0.20969728  0.12450776]
   [-0.0982956   0.01965912]
   [-0.15727296 -0.15071991]]

  [[ 0.18348512  0.12450776]
   [-0.09174256 -0.11795472]
   [-0.20314424 -0.24901551]
   [ 0.04587128 -0.0327652 ]
   [ 0.28833374  0.17037904]]

  [[-0.23590943 -0.1965912 ]
   [-0.03931824  0.05897736]
   [ 0.1965912   0.2293564 ]
   [-0.05897736 -0.0655304 ]
   [-0.33420503 -0.2621216 ]]

  [[-0.07208344  0.2948868 ]
   [-0.24246247  0.12450776]
   [-0.3604172  -0.13761383]
   [-0.04587128  0.14416687]
   [ 0.05242432  0.37352327]]

  [[-0.63564485 -0.37352327]
   [-0.4456067  -0.39973542]
   [-0.18348512  0.05897736]
   [-0.33420503 -0.30799288]
   [-0.7077283  -0.3473111 ]]]][C7x_1 ] 433297.143915 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.143957 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced

[C7x_1 ] 433297.144001 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.144054 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.144097 s: Core 0 Alg Process for Layer # -    1, layer type 1
[C7x_1 ] 433297.144126 s: Processing Layer # -    1
[C7x_1 ] 433297.144189 s: Core 0 End of Layer # -    1 with outPtrs[0] = a318d000
[C7x_1 ] 433297.144227 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.144274 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
[C7x_1 ] 433297.144320 s: PREEMPTION: Requesting LOCK for priroty object with handle = b2875f40 and targetPriority 0
[C7x_1 ] 433297.144371 s: PREEMPTION: Request of LOCK for priroty object with handle = b2875f40 and targetPriority 0 is serviced with state 0
[C7x_1 ] 433297.144411 s: TIDL_process is completed with handle : b2875f40
[C7x_1 ] 433297.144445 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0
[C7x_1 ] 433297.144486 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 0 is serviced
************ in ~tidlDelegate ************
 ************ in TIDL_subgraphRtDelete ************
 APP: Deinit ... !!!
REMOTE_SERVICE: Deinit ... !!!
REMOTE_SERVICE: Deinit ... Done !!!
433297.197754 s: IPC: Deinit ... !!!
433297.198295 s: IPC: DeInit ... Done !!!
433297.198351 s: MEM: Deinit ... !!!
433297.198366 s: DDR_SHARED_MEM: Alloc's: 7 alloc's of 1605922 bytes
433297.198375 s: DDR_SHARED_MEM: Free's : 7 free's  of 1605922 bytes
433297.198382 s: DDR_SHARED_MEM: Open's : 0 allocs  of 0 bytes
433297.198398 s: MEM: Deinit ... Done !!!
APP: Deinit ... Done !!!
[C7x_1 ] 433297.191460 s: TIDL_deactivate is called with handle : b2875f40 - Copying handle of size 19736 from 7e0f2000 to b2875f40
[C7x_1 ] 433297.191581 s: PREEMPTION: Removing priroty object with handle = b2875f40 and targetPriority = 0,      Number of obejcts left are = 1, removed object with base  = b28fd700 and size =128
root@am62axx-evm:/tmp/5826.custom/custom#

So your artifacts are valid and there are indeed no errors coming through.

The question remains why your installation is running into errors here. It is not the artifacts.

Assuming you are also on the 10.1 SDK, have you made any modifications to libraries or other SDK components? This is running the standard SDK installed from the official page: https://www.ti.com/tool/PROCESSOR-SDK-AM62A ? And you are running on our EVM or custom hardware?

Perhaps it is worth re-flashing your SD card to start fresh. If you haven't yet, also reboot the EVM.

BR,
Reese

0 Sopheap Key 4 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I received EVM am62a7 from a collegue where SDK is already installed. The version is 10.00.xx.xx has been installed on that EVM. Is it necessary to run everything tidl tool and sdk on version 10.1?

After I compiled the model using tidl tool version 10.00.xx.xx on my local PC, the inference was working fine without TIDL graph error just like the one you showed.

Regards,

Key

0 Reese Grimsley 4 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Yes, the SDK, tidl tools, and model artifacts must all be for the same SDK.

I typically see more clear messages in the output logs that indicate some version mismatch. This would show from the vx_app_arm_remote_log.out utility, and must be running in the background before starting inference with debug_level=2.

Relevant FAQ: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1455079/faq-edge-ai-studio-is-sdk-version-important-for-edge-ai-and-ti-deep-learning-tidl-with-c7x-on-am6xa-socs-am62a-am67a-am68a-am68pa-am69a

There is a way to upgrade your EVM/SDK installation to use 10.1 compatible tools on 10.0 with a backwards-compatibility feature. I can tell more about this if necessary, but will otherwise recommend reinstalling with 10.1 SDK.

BR,
Reese

0 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

Thank you for this useful information.

I compiled my custom model and I got several error message. Please have a look at below file. It is regarding to the size.

Fullscreen 2110.log_message.txt Download

tidl_tools_path                                 = /home/key/edgeai-tidl-tools-rel_10_00/tidl_tools
artifacts_folder                                = ./model-artifacts/
tidl_tensor_bits                                = 8
debug_level                                     = 2
num_tidl_subgraphs                              = 16
tidl_denylist                                   =
tidl_denylist_layer_name                        =
tidl_denylist_layer_type                        =
tidl_allowlist_layer_name                       =
model_type                                      =
tidl_calibration_accuracy_level                 = 7
tidl_calibration_options:num_frames_calibration = 20
tidl_calibration_options:bias_calibration_iterations = 50
mixed_precision_factor = -1.000000
model_group_id = 0
power_of_2_quantization                         = 2
ONNX QDQ Enabled                                = 0
enable_high_resolution_optimization             = 0
pre_batchnorm_fold                              = 1
add_data_convert_ops                            = 0
output_feature_16bit_names_list                 =
m_params_16bit_names_list                       =
m_single_core_layers_names_list                 =
Inference mode                                  = 0
Number of cores                                 = 1
reserved_compile_constraints_flag               = 1601
partial_init_during_compile                     = 0
ti_internal_reserved_1                          =

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              10_00_08_00             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              10_00_02_00             |
-------------------------------------------------------------------------------

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- sequential_1/re_lu_1/Relu;sequential_1/conv2d_1/BiasAdd;sequential_1/conv2d_1/convolution;1  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 2 Tflite layer type --- 17 layer output name--- sequential_1/max_pooling2d_1/MaxPool2d  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- sequential_1/re_lu_1_2/Relu;sequential_1/conv2d_1_2/BiasAdd;sequential_1/conv2d_1_2/convolution;sequential_1/conv2d_1_2/Squeeze  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 2 Tflite layer type --- 17 layer output name--- sequential_1/max_pooling2d_1_2/MaxPool2d  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 38 Tflite layer type --- 22 layer output name--- sequential_1/flatten_1/Reshape  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import]  WARNING: Size larger than (2048*2048) in [] is not optimal
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 6 Tflite layer type --- 9 layer output name--- sequential_1/dense_1/MatMul;sequential_1/re_lu_2_1/Relu;sequential_1/dense_1/BiasAdd  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 6 Tflite layer type --- 9 layer output name--- sequential_1/dense_1_2/MatMul;sequential_1/dense_1_2/BiasAdd  -- [tidl_tfLiteRtImport_core.cpp, 3090]
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 7 Tflite layer type --- 25 layer output name--- StatefulPartitionedCall_1:0  -- [tidl_tfLiteRtImport_core.cpp, 3090]

Total Nodes = 8
-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       8 |                       1 |
| CPU                     |                       0 |                       x |
-------------------------------------------------------------------------------
============================= [Parsing Completed] =============================

In TIDL_tfliteRtImportInit subgraph_id=17
Layer 0, subgraph id 17, name=StatefulPartitionedCall_1:0
Layer 1, subgraph id 17, name=serving_default_keras_tensor:0
In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3
In TIDL_tfliteRtImportNode, TIDL Layer type - 2, Tflite builtin code type - 17
In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3
In TIDL_tfliteRtImportNode, TIDL Layer type - 2, Tflite builtin code type - 17
In TIDL_tfliteRtImportNode, TIDL Layer type - 38, Tflite builtin code type - 22
In TIDL_tfliteRtImportNode, TIDL Layer type - 6, Tflite builtin code type - 9
In TIDL_tfliteRtImportNode, TIDL Layer type - 6, Tflite builtin code type - 9
In TIDL_tfliteRtImportNode, TIDL Layer type - 7, Tflite builtin code type - 25
==================== [Optimization for subgraph_17 started] ====================

In TIDL_runtimesOptimizeNet: LayerIndex = 10, dataIndex = 9
----------------------------- Optimization Summary -----------------------------
---------------------------------------------------------------------------------
|          Layer         | Nodes before optimization | Nodes after optimization |
---------------------------------------------------------------------------------
| TIDL_SoftMaxLayer      |                         1 |                        1 |
| TIDL_InnerProductLayer |                         2 |                        2 |
| TIDL_CropLayer         |                         0 |                        2 |
| TIDL_ConvolutionLayer  |                         2 |                        2 |
| TIDL_PoolingLayer      |                         2 |                        2 |
---------------------------------------------------------------------------------

=================== [Optimization for subgraph_17 completed] ===================

In TIDL_runtimesPostProcessNet
[TIDL Import] [PARSER] UNSUPPORTED: All the tensor dimensions has to be greater then zero. For tensor sequential_1/flatten_1/Reshape_6, id 8 - Dim 4 is 0 -- [tidl_import_common_model_check.cpp, 2310]
[TIDL Import]  WARNING: Size larger than (2048*2048) in [sequential_1/dense_1/MatMul;sequential_1/re_lu_2_1/Relu;sequential_1/dense_1/BiasAdd] is not optimal
************ in TIDL_subgraphRtCreate ************
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.2s:  VX_ZONE_ERROR:Enabled
 0.3s:  VX_ZONE_WARNING:Enabled
 0.2193s:  VX_ZONE_INIT:[tivxInit:190] Initialization Done !!!
 0.25942s:  VX_ZONE_ERROR:[tivxMemBufferAlloc:130] size is 0
 0.25974s:  VX_ZONE_ERROR:[ownAllocReferenceBufferGeneric:340] Memory allocation failed
 0.25975s:  VX_ZONE_ERROR:[ownGraphAllocateDataObject:1031] Memory allocation for data reference failed
 0.25976s:  VX_ZONE_ERROR:[vxVerifyGraph:2199] Memory alloc for data objects failed
 0.25977s:  VX_ZONE_ERROR:[vxVerifyGraph:2311] Graph verify failed
TIDL_RT_OVX: ERROR: Verifying TIDL graph ... Failed !!!
TIDL_RT_OVX: ERROR: Verify OpenVX graph failed
************ TIDL_subgraphRtCreate done ************
 tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.29978s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.29994s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.30000s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 1196.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 1 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0014s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.30383s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.30394s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.30395s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 39.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 2 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.30664s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.30674s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.30675s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 3 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.30922s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.30932s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.30934s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 4 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.31163s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.31174s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.31175s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 5 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.31420s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.31431s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.31432s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 37.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 6 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.31662s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.31672s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.31673s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 7 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.31899s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.31909s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.31910s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 8 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.32129s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.32139s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.32140s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 9 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.32363s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.32373s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.32374s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 10 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.32590s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.32600s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.32601s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 11 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.32818s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.32828s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.32829s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 12 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.33070s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.33080s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.33081s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 13 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.33338s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.33348s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.33350s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 14 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.33575s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.33585s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.33587s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 15 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.33804s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.33814s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.33815s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 16 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.34029s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.34039s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.34040s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 17 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.34254s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.34264s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.34265s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 18 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.34487s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.34497s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.34498s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 36.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 19 : Running float inference ****************

tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 0.0002s
tidl_tfLiteRtImport_delegate.cpp Invoke 526
*******   In TIDL_subgraphRtInvoke  ********
 0.34720s:  VX_ZONE_ERROR:[ownTensorCheckSizes:119] Invalid view parameter(s) in dimension: 1
 0.34730s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:761] map address is null
 0.34731s:  VX_ZONE_ERROR:[tivxUnmapTensorPatch:765] map size is equal to 0
ERROR: Running TIDL graph ... Failed !!!
Sub Graph Stats 35.000000 28391.000000 11372118583172728.000000
*******  TIDL_subgraphRtInvoke done  ********

 ************ Frame index 20 : Running fixed point mode for calibration ****************

In TIDL_runtimesPostProcessNet

-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
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==================== [Quantization & Calibration Completed] ====================

[TIDL Import] [PARSER] UNSUPPORTED: All the tensor dimensions has to be greater then zero. For tensor sequential_1/flatten_1/Reshape_6, id 8 - Dim 4 is 0 -- [tidl_import_common_model_check.cpp, 2310]
[TIDL Import]  WARNING: Size larger than (2048*2048) in [sequential_1/dense_1/MatMul;sequential_1/re_lu_2_1/Relu;sequential_1/dense_1/BiasAdd] is not optimal
[TIDL Import] [PARSER] WARNING:
********************************************************************
*     Network compiler returned with error or didn't executed      *
*      This model can only be used on PC/Host emulation mode       *
*            It is not expected to work on target/EVM              *
********************************************************************

======================== Subgraph Compiled Successfully ========================


 Final number of subgraphs:1 , 8 nodes delegated to accelerator

Running Runtimes GraphViz - /home/key/edgeai-tidl-tools-rel_10_00/tidl_tools/tidl_graphVisualiser_runtimes.out ./model-artifacts//allowedNode.txt ./model-artifacts//tempDir/graphvizInfo.txt ./model-artifacts//tempDir/runtimes_visualization.svg
tidl_tfLiteRtImport_delegate.cpp Invoke 647
time invoked: 183.2707s
Output:
[[0 0]]
************ in TIDL_subgraphRtDelete ************
 MEM: Deinit ... !!!
MEM: Alloc's: 6 alloc's of 59600052 bytes
MEM: Free's : 6 free's  of 59600052 bytes
MEM: Open's : 0 allocs  of 0 bytes
MEM: Deinit ... Done !!!

Regards,
Key

0 Reese Grimsley 3 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hello,

Right, I see the lines that concerns me:

>54: [TIDL Import] WARNING: Size larger than (2048*2048) in [] is not optimal

>96: [TIDL Import] [PARSER] UNSUPPORTED: All the tensor dimensions has to be greater then zero. For tensor sequential_1/flatten_1/Reshape_6, id 8 - Dim 4 is 0 -- [tidl_import_common_model_check.cpp, 2310]

>97: [TIDL Import] WARNING: Size larger than (2048*2048) in [sequential_1/dense_1/MatMul;sequential_1/re_lu_2_1/Relu;sequential_1/dense_1/BiasAdd] is not optimal

It looks like you have a very large MatMul (>>2048^2). Is this correct?

Otherwise, I suspect the Reshape dimension being 0 is confusing our model parser. If you do not need a dimension, then that value should be omitted (e.g. 3 dimension values instead of 4, like [1,256,256,0] should be [1,256,256]). Sometimes shapes are parsed incorrectly, and the assumed values are far larger than the model actually uses. This can lead to extremely large tensor dimensions and show errors like the above.

The compile log here is confirming that the issue is during the compilation stage, and is related to how your model was parsed.

Does your model actually have such a large MatMul? If so, that will need to be trimmed to a smaller size for TIDL to import and run the model

BR,
Reese

0 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I modify the dimension of model and it did not show the previous message.
However, I got another warning regarding calibration during tidl compilation.
I quantized keras (float32) to tflite (int8) prior to importing tflite model to tidl tools. I saw a warning during compilation tflite model as shown in txt file below.

4786.log.txt

This is the message log when I do the inference script. It showed one of the node is not offloaded to c7x.

1832.output.log

Regards,

Key

0 Reese Grimsley 3 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hello,

You have one unsupported layer:

----------------------------------------------------------------------------------------------------------------------------------------------
| Node |                    Node Name                    |                                      Reason                                       |
----------------------------------------------------------------------------------------------------------------------------------------------
| MEAN | functional_31_1/global_average_pooling2d_1/Mean | 3x3,2x2s,1x1 with stride 1 and stride 2 (both horizontal and vertical dimensions) |
----------------------------------------------------------------------------------------------------------------------------------------------

This is a case where a layer configuration may not be supported, e.g. large average pool kernel. The supported layer configurations are listed in the documentation for this repo:

https://github.com/TexasInstruments/edgeai-tidl-tools/blob/rel_10_00/docs/supported_ops_rts_versions.md
- Link to 10.0 SDK version of the doc

Is yours a global average pool, as the name suggests?

The other warnings are related to calibration not being sufficient. This looks like it was coming from the second subgraph. It probably means that some data resulting from the first subgraph + non-offloaded-node was not complete enough for the second subgraph's calibration-input data.

My recommendation to proceed would be to modify that unsupported MEAN layer to be a supported version. For large kernel sizes (e.g. 9x9), standard practice is to modify the network architecture such that this is implemented by a series of smaller kernel sizes. We routinely do this with large maxpools in ONNX networks:

https://github.com/TexasInstruments/edgeai-tidl-tools/blob/95ba2c7ec62bbedeb637d7a5c0273fcede21cac9/osrt-model-tools/osrt_model_tools/onnx_tools/tidl_onnx_model_optimizer/src/maxpool.py#L68
- ONNX networks are much easier to directly modify than tflite.

BR,
Reese

0 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

The error is regarding to maxpooling stride which I set pool_size of (3,3) and leave stride size empty. Once I set pool size and stride size to (2,2), it worked wonderfully. I have another concern regarding the conversion from keras model to onnx model. There is a library that makes job done. Is it a good consideration?

I use pytorch trying to convert and quantize to INT8. However, the scale outputs from every layer are shown in FLOAT and some zero points are in INT32 as shown in txt file below. Did I quantize correctly?

Fullscreen 0435.log.txt Download

input_zero_point: INT8
input_scale: FLOAT
conv1.weight_zero_point: INT8
conv1.weight_scale: FLOAT
conv1.weight_quantized: INT8
/relu/Relu_output_0_zero_point: INT8
/relu/Relu_output_0_scale: FLOAT
conv2.weight_zero_point: INT8
conv2.weight_scale: FLOAT
conv2.weight_quantized: INT8
/relu_1/Relu_output_0_zero_point: INT8
/relu_1/Relu_output_0_scale: FLOAT
/gap/GlobalAveragePool_output_0_zero_point: INT8
/gap/GlobalAveragePool_output_0_scale: FLOAT
fc1.weight_zero_point: INT8
fc1.weight_scale: FLOAT
fc1.weight_quantized: INT8
/relu_2/Relu_output_0_zero_point: INT8
/relu_2/Relu_output_0_scale: FLOAT
/fc2/Gemm_output_0_zero_point: INT8
/fc2/Gemm_output_0_scale: FLOAT
fc2.weight_zero_point: INT8
fc2.weight_scale: FLOAT
fc2.weight_quantized: INT8
output_zero_point: INT8
output_scale: FLOAT
conv1.bias_quantized: INT32
conv1.bias_quantized_scale: FLOAT
conv1.bias_quantized_zero_point: INT32
conv2.bias_quantized: INT32
conv2.bias_quantized_scale: FLOAT
conv2.bias_quantized_zero_point: INT32
fc1.bias_quantized: INT32
fc1.bias_quantized_scale: FLOAT
fc1.bias_quantized_zero_point: INT32
fc2.bias_quantized: INT32
fc2.bias_quantized_scale: FLOAT
fc2.bias_quantized_zero_point: INT32

Regards,
Key

0 Reese Grimsley 3 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Glad to know that Pooling layer change worked :)

Sopheap Key said:
I have another concern regarding the conversion from keras model to onnx model. There is a library that makes job done. Is it a good consideration?

In general yes such tools are okay, but I find that model-export from one format to another can add some odd layers that technically implements the same function, but in a strange fashion. For simple networks, this is likely fine, and is certainly worth trying.

I find that the onnxsim (onnx-simplifier) is good for cleaning up the network, especially after export/format-change. This can be especially helpful when some dimensions like 'batch' are not fixed dimensions and instead use more operators / layers to handle such dynamic dimensions.

Another tool for your awareness is TI's own model-optimization scripts for ONNX-models. This can apply a series of rules to find common scenarios in ONNX models, where we can replace some layers/configurations with an alternate that is easier to parse/accelerate.

https://github.com/TexasInstruments/edgeai-tidl-tools/tree/master/osrt-model-tools/osrt_model_tools/onnx_tools/tidl_onnx_model_optimizer

Sopheap Key said:
I use pytorch trying to convert and quantize to INT8. However, the scale outputs from every layer are shown in FLOAT and some zero points are in INT32 as shown in txt file below. Did I quantize correctly?

Quantized scale would be a float32, yes. I'm inclined to say the zero-points should be integers and that the data-type of int8 vs. int32 is okay at this stage.

Our quantization tools support ONNX QDQ and TFlite quantized models. You will need to export your PyTorch model into ONNX QDQ format.

For you reference, here is our quantization aware-training (QAT) documentation:

https://github.com/TexasInstruments/edgeai-tensorlab/blob/main/edgeai-modeloptimization/torchmodelopt/edgeai_torchmodelopt/xmodelopt/quantization/README.md

BR,
Reese

0 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

Is QAT preferred over PTQ? Currently, I am quantizing using PTQ.

I have another concern regarding the benchmark output of tflite model during compilation and inference using below function from TIDL Tools. I want to check how much time is offloaded to C7x; however, it returns 0. When I tried to check for subgraphIds during inference, there is none (_proc_end, _proc_start, and etc). It just showed as shown in figure below. Have I missed on something important during quantization or compilation?

def get_benchmark_output(interpreter):

'''

Returns benchmark data

:param interpreter: Runtime session

:return: Copy time

:return: Total time

:return: Processing time

:return: Write time

:return: Read time

'''

benchmark_dict = interpreter.get_TI_benchmark_data()

proc_time = copy_time = 0

cp_in_time = cp_out_time = 0

subgraphIds = []

for stat in benchmark_dict.keys():

print(stat)

if "proc_start" in stat:

subgraphIds.append(int(re.sub("[^0-9]", "", stat)))

for i in range(len(subgraphIds)):

proc_time += (

benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_proc_end"]

- benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_proc_start"]

)

cp_in_time += (

benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_copy_in_end"]

- benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_copy_in_start"]

)

cp_out_time += (

benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_copy_out_end"]

- benchmark_dict["ts:subgraph_" + str(subgraphIds[i]) + "_copy_out_start"]

)

copy_time += cp_in_time + cp_out_time

print(proc_time)

write_total = benchmark_dict["ddr:read_end"] - benchmark_dict["ddr:read_start"]

read_total = benchmark_dict["ddr:write_end"] - benchmark_dict["ddr:write_start"]

totaltime = benchmark_dict["ts:run_end"] - benchmark_dict["ts:run_start"]

copy_time = copy_time if len(subgraphIds) == 1 else 0

return copy_time, totaltime, proc_time, write_total / 1000000, read_total / 1000000

Regards,
Key

0 Reese Grimsley 3 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Sopheap Key said:
Is QAT preferred over PTQ? Currently, I am quantizing using PTQ.

There's a balance of effort vs. benefit here

QAT is generally expected to provide higher accuracy since training/backprop is in the loop, but this requires more effort.

PTQ is often good-enough (1-2% of error) on a well-trained model, meaning that the architecture follows guidelines like at the link shown:

https://github.com/TexasInstruments/edgeai-tensorlab/blob/main/edgeai-modeloptimization/torchmodelopt/edgeai_torchmodelopt/xmodelopt/quantization/docs/guidelines.md
If PTQ is good enough for your use-case, then makes sense to only use this (potentially with some mixed-precision for sensitive layers like last convolutions)
Follow guidelines above for your model architecture before resorting to QAT

Sopheap Key said:
I want to check how much time is offloaded to C7x; however, it returns 0.

So this get_TI_benchmark_data() is giving a dictionary with only 0's as values? Are you running on the target SOC or on PC?

If you are on the target, please supply the printout of your inference command. We should see something like the following, at a minimum:
- Number of subgraphs:1 , 1 nodes delegated out of 1 nodes

We can provide bit-accurate outputs on PC with emulation, but not accuracy estimates. The C7xMMA emulator is bit-accurate but not cycle-accurate.

BR,
Reese

0 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

I run it on PC to check out the performance benchmark. get_TI_benchmark_data() gives (run_start, run_end, read_start, read_end, write_start, and write_end) only during both compilation and inference, and offload time 0. I tried the model from TIDL Tools (mobilenet, or inception), and the total run time and offload time are display. Below figure is a list of inference on mobilenetv1 (subgraphs and benchmark output).

Regards,
Key

0 Reese Grimsley 3 months ago in reply to Sopheap Key

TI__Genius 15616 points

Hi Key,

Okay, this is expected behavior, then

That get_TI_benchmark_data() will return a correctly formed dictionary of data, but since the tool is not cycle-accurate on PC, it will return data that is not indicative of the achievable performance. To get performance information, you will need to run this on the target.

It can still collect this runtime information for the same interfaces on PC, but it will be CPU-time for the PC. This will be much slower than the target's accelerator

BR,
Reese

+1 Sopheap Key 3 months ago in reply to Reese Grimsley

Prodigy 210 points

Hello Reese,

Thank you for your guidance and feedback.
I will end this thread since I have already achieved what I have asked. I will open a new thread if I face another problem.

Best regards,

Key

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