TDA4VEN-Q1: PCB Trace of OSPI0_LBCLK

Furuna Yamamoto

Prodigy 250 points

Part Number: TDA4VEN-Q1

Tool/software:

Please teach us about the design policy for "OSPI0_LBCLK".

I understand that the PHY mode supports four clocking topologies for the receive data capture clock.

If DQS mode is used, does LBCLK need to be pattern designed?

(OSPI0_LBCLK is N.C. or pull-up/down)

3 months ago

0 Robert Eschler 3 months ago

TI__Guru 52125 points

If the connecting memory peripheral supports DQS output, then LBCLK is not needed. If connecting memory does NOT support DQS, the LBCLK should be connected to DQS with a trace length equal twice the length to memory device (route to memory device and back to DQS pin).

0 Furuna Yamamoto 3 months ago in reply to Robert Eschler

Prodigy 250 points

Thank you for your answer.

We confirmed that the connecting memory has DS(DQS) signal. So, We connect the SoC DQS signal pin to the memory DS pin.

At that time, is the SoC LBCLK pin N.C.?

0 Furuna Yamamoto 3 months ago in reply to Furuna Yamamoto

Prodigy 250 points

Hi. Robert-san,

Please answer the following question.

> At that time, is the SoC LBCLK pin N.C.?

Regards,

+1 Robert Eschler 3 months ago in reply to Furuna Yamamoto

TI__Guru 52125 points

Yes - LBCLK is not used when DQS is supported - thus it can be N.C.

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TDA4VEN-Q1: PCB Trace of OSPI0_LBCLK