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TDA4VM: Sciclient_init is blocked when using IPCLLD

Part Number: TDA4VM

Tool/software:

Hello, experts

I want to test the IPC driver provided in the RTOS SDK on my J721E. However, during this process, I found that the program for testing IPC would be blocked when calling Sciclient_init, which prevented me from testing the IPC driver.

When testing the IPC driver, I hope to achieve the following functions:

mcu1_1(baremetal) sends a msg to mcu2_0(baremetal) through the IPC driver

In order to achieve the above-mentioned functions, I referred to 4.11.9.Writing HelloWorld App using IPCLLD

I also referred  to the < PDK_INSTALL_PATH >/packages/ti/drv/ipc/examples/common/src/ipc_testsetup_baremetal.c file

I have respectively written two test codes, ipc_test_mcu1_1.c and ipc_test_mcu2_0.c, as follows:

/*
* ipc_test_mcu1_1.c
*/
#include <stdint.h>
#include <ti/board/board.h>
#include <ti/csl/tistdtypes.h>
#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
#include <ti/drv/ipc/ipc.h>
#include <ti/drv/ipc/soc/V1/ipc_soc.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/drv/uart/UART_stdio.h>

uint32_t virt2phy_func(const void *virtAddr) { return ((uint32_t)virtAddr); }
void *phy2virt_func(uint32_t phyAddr) {
  uint32_t temp = phyAddr;
  return ((void *)temp);
}
void newmsg_callback_func(uint32_t srcEndPt, uint32_t procId) { return; }
void uart_print(const char *str) {
  UART_printf("%s", str);
  return;
}

uint8_t vqBuf[VQ_BUF_SIZE]
    __attribute__((section("my_ipc_data_buffer"), aligned(8)));
uint8_t selfBuf[RPMSG_DATA_SIZE]
    __attribute__((section("my_ipc_data_buffer"), aligned(8)));

int main(void) {
  Sciclient_ConfigPrms_t config;
  Sciclient_configPrmsInit(&config);
  Sciclient_init(&config);

  Board_initCfg boardCfg;
  boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO;
  Board_init(boardCfg);

  UART_printf("IPC_echo_test mcu1_1\n");

  uint32_t numProc = 1;
  uint32_t pRemoteProcArray[] = {IPC_MCU2_0};
  uint32_t selfProcId = IPC_MCU1_1;

  uint32_t selfPt = 10;
  uint32_t remotePt = 10;
  uint32_t remoteProcId = IPC_MCU2_0;

  Ipc_InitPrms initPrms;
  Ipc_VirtIoParams vqParam;

  /* Step1 : Initialize the multiproc */
  if (IPC_SOK == Ipc_mpSetConfig(selfProcId, numProc, pRemoteProcArray)) {
    UART_printf("IPC_echo_test (core : %s) .....\r\n", Ipc_mpGetSelfName());

    /* Initialize params with defaults */
    IpcInitPrms_init(0U, &initPrms);

    initPrms.newMsgFxn = &newmsg_callback_func;
    initPrms.virtToPhyFxn = &virt2phy_func;
    initPrms.phyToVirtFxn = &phy2virt_func;
    initPrms.printFxn = &uart_print;

    if (IPC_SOK != Ipc_init(&initPrms)) {
      return -1;
    }
  } else {
    UART_printf("Ipc_mpSetConfig failed\n");
  }

  /* Step2 : Initialize Virtio */
  vqParam.vqObjBaseAddr = (void *)vqBuf;
  vqParam.vqBufSize = numProc * Ipc_getVqObjMemoryRequiredPerCore();
  vqParam.vringBaseAddr = (void *)VRING_BASE_ADDRESS;
  vqParam.vringBufSize = IPC_VRING_BUFFER_SIZE;
  vqParam.timeoutCnt = 100; /* Wait for counts */
  Ipc_initVirtIO(&vqParam);

  /* Step 3: Initialize RPMessage */
  RPMessage_Params selfRPMsgParam;
  RPMessageParams_init(&selfRPMsgParam);

  selfRPMsgParam.buf = selfBuf;
  selfRPMsgParam.bufSize = RPMSG_DATA_SIZE;
  selfRPMsgParam.stackBuffer = NULL;
  selfRPMsgParam.stackSize = 0U;
  selfRPMsgParam.requestedEndpt = remotePt;

  RPMessage_init(&selfRPMsgParam);
  RPMessage_Handle selfRPMsgHandle;
  selfRPMsgHandle = RPMessage_create(&selfRPMsgParam, &selfPt);

  char sendMsg[256] = "hello from mcu1_1";
  uint32_t msgLen = strlen(sendMsg);

  int32_t status = RPMessage_send(selfRPMsgHandle, remoteProcId, remotePt,
                                  selfPt, (void *)sendMsg, msgLen);
  if (status != IPC_SOK) {
    UART_printf("Failed: RPMessage %s ----> %s\nMsg: %s\n", Ipc_mpGetSelfName(),
                Ipc_mpGetName(remoteProcId), sendMsg);
  } else {
    UART_printf("Success: RPMessage %s ----> %s\nMsg: %s\n",
                Ipc_mpGetSelfName(), Ipc_mpGetName(remoteProcId), sendMsg);
  }
  return (0);
}
/*
* ipc_test_mcu2_0.c
*/
#include <stdint.h>
#include <ti/board/board.h>
#include <ti/csl/tistdtypes.h>
#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
#include <ti/drv/ipc/ipc.h>
#include <ti/drv/ipc/soc/V1/ipc_soc.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/drv/uart/UART_stdio.h>

uint32_t virt2phy_func(const void *virtAddr) { return ((uint32_t)virtAddr); }
void *phy2virt_func(uint32_t phyAddr) {
  uint32_t temp = phyAddr;
  return ((void *)temp);
}
void newmsg_callback_func(uint32_t srcEndPt, uint32_t procId) { return; }
void uart_print(const char *str) {
  UART_printf("%s", str);
  return;
}

uint8_t vqBuf[VQ_BUF_SIZE]
    __attribute__((section("my_ipc_data_buffer"), aligned(8)));
uint8_t selfBuf[RPMSG_DATA_SIZE]
    __attribute__((section("my_ipc_data_buffer"), aligned(8)));

int main(void) {
  Sciclient_ConfigPrms_t config;
  Sciclient_configPrmsInit(&config);
  Sciclient_init(&config);

  Board_initCfg boardCfg;
  boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO;
  Board_init(boardCfg);

  UART_printf("IPC_echo_test mcu2_0\n");

  uint32_t numProc = 1;
  uint32_t pRemoteProcArray[] = {IPC_MCU1_1};
  uint32_t selfProcId = IPC_MCU2_0;

  uint32_t selfPt = 10;
  uint32_t remotePt = 10;
  uint32_t remoteProcId = IPC_MCU1_1;

  Ipc_InitPrms initPrms;
  Ipc_VirtIoParams vqParam;

  /* Step1 : Initialize the multiproc */
  if (IPC_SOK == Ipc_mpSetConfig(selfProcId, numProc, pRemoteProcArray)) {
    UART_printf("IPC_echo_test (core : %s) .....\r\n", Ipc_mpGetSelfName());

    /* Initialize params with defaults */
    IpcInitPrms_init(0U, &initPrms);

    initPrms.newMsgFxn = &newmsg_callback_func;
    initPrms.virtToPhyFxn = &virt2phy_func;
    initPrms.phyToVirtFxn = &phy2virt_func;
    initPrms.printFxn = &uart_print;

    if (IPC_SOK != Ipc_init(&initPrms)) {
      return -1;
    }
  } else {
    UART_printf("Ipc_mpSetConfig failed\n");
  }

  /* Step2 : Initialize Virtio */
  vqParam.vqObjBaseAddr = (void *)vqBuf;
  vqParam.vqBufSize = numProc * Ipc_getVqObjMemoryRequiredPerCore();
  vqParam.vringBaseAddr = (void *)VRING_BASE_ADDRESS;
  vqParam.vringBufSize = IPC_VRING_BUFFER_SIZE;
  vqParam.timeoutCnt = 100; /* Wait for counts */
  Ipc_initVirtIO(&vqParam);

  /* Step 3: Initialize RPMessage */
  RPMessage_Params selfRPMsgParam;
  RPMessageParams_init(&selfRPMsgParam);

  selfRPMsgParam.buf = selfBuf;
  selfRPMsgParam.bufSize = RPMSG_DATA_SIZE;
  selfRPMsgParam.stackBuffer = NULL;
  selfRPMsgParam.stackSize = 0U;
  selfRPMsgParam.requestedEndpt = remotePt;

  RPMessage_init(&selfRPMsgParam);
  RPMessage_Handle selfRPMsgHandle;
  selfRPMsgHandle = RPMessage_create(&selfRPMsgParam, &selfPt);

  char recvMsg[256] = {0};
  uint16_t msgLen = strlen(recvMsg);
 
  int32_t status = RPMessage_recv(selfRPMsgHandle, recvMsg, &msgLen,
                                  &remotePt, &remoteProcId, IPC_RPMESSAGE_TIMEOUT_FOREVER);
  if (status != IPC_SOK) {
    UART_printf("Failed: RPMessage %s <---- %s\nMsg: %s\n", Ipc_mpGetSelfName(),
                Ipc_mpGetName(remoteProcId), recvMsg);
  } else {
    UART_printf("Success: RPMessage %s <---- %s\nMsg: %s\n",
                Ipc_mpGetSelfName(), Ipc_mpGetName(remoteProcId), recvMsg);
  }
  return (0);
}

After successfully compiling the above code, I debugged the above code through CCS

The basic debugging process is:

1.Refer to EVM Setup for J721E to configure J721E
2.Refer to CCS Setup for J721E to successfully connect to J721E using CCS
3.Run the  sciserver_testapp program in mcu1_0
4.Run the  ipc_test_mcu2_0 program in mcu2_0
5.Run the  ipc_test_mcu1_1 program on mcu1_1

During the debugging process, both  ipc_test_mcu1_1 and  ipc_test_mcu2_0 will be blocked in the  Sciclient_init statement, causing the program to fail to execute normally

I want to ask the experts why my program is blocking to Sciclient_init?

How should I modify my program so that it can execute normally?

The version of SDK I'm using is:PROCESSOR-SDK-RTOS-J721E —10.00.00.05

  • Hello,

    Sciclient is blocked means sciserver is not running properly on MCU1_0 core.Please check inside sciclient_init() it got blocked.

    Note: I will be on leave till next Tuesday please expect delay.

    Regards

    Tarun Mukesh 

  • Thanks for your reply, but the sciserver_testapp running on mcu1_0 is from the example in the RTOS SDK, and the UART serial output indicates that the sciserver is working properly.

    Also, when executing the same sciserver_testapp program on mcu1_0, if executing other non-IPC related programs on mcu1_1 or mcu2_0, such as sciclient_unit_testapp_freertos, Then the program will not be blocked to the Sciclient_init statement.

    Is it because sciserver needs additional configuration when a program needs to call the IPC driver? However, it seems that this point is not mentioned in the introduction of IPCLLD.

  • Hello,

    Thats strange. NO additional call is needed for IPC .All sciclient_init calls are the same it has nothing to do with IPC.

    I tried running ipc test application in EVM and it is not blocking for me during sciclient_init call.

    May i know where exactly inside the sciclient_init call it is blocking ?

    Regards

    Tarun Mukesh

  • The call stack of the program is shown in the figure.

  • It seems that the program got stuck because it couldn't receive some messages.

  • Hi,

    It seems like the SCIServer is not running properly. I am doubting that the memory allocated for the two baremetal app could have overwritten the SCIServer app. Could you please provide the linker command file of  both  ipc_test_mcu1_1 and  ipc_test_mcu2_0. Also, the respective generated .map files

    Regards,

    Karthik

  • Thank you for your reply. I have packed all the files you might need into the attachment file.

    The map files for ipc_test_mcu1_1, ipc_test_mcu2_0, and sciserver are located in the binary folder.
    The source codes corresponding to ipc_test_mcu1_1, ipc_test_mcu2_0 and sciserver, the makefile file containing linker commands, and the corresponding lds files are all stored in the src folder.
    The lds files used to build ipc_test_mcu1_1 and ipc_test_mcu2_0 are located in the ./ipc_common/j721e directory.

    8400.attachment.zip

  • Hi,

    On a quick analysis we have observed the following from the source which you have shared.

    1. The SciServer application that loads on MCU1_0 was built in debug mode. When in debug mode it does require more memory and I could see you have moved some of the bss section into the SBL_USED_OCMC_RAM. Also, the size of the SCIServer app built in debug mode is less than 3MB which is lesser than the size of SCIServer app built in release mode. I advise you to build  SCIServer in release mode using linker_r5_freertos_release.lds. With this approach we are able to execute your application successfully.

    Please clarify why do you need to build SciServer application in debug mode.

    Regards

    Karthik

  • Hi,

    I use the debug mode when building the sciserver running on mcu1_0 because I want to debug the sciserver in CCS.

    The prebuilt sciserver in <PDK_PATH>/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/sciserver_testapp_freertos_mcu1_0_release.xer5f cannot view the corresponding source code when debugging through CCS.

    I didn't change the source code, the makfile command, or the lds file while building the debug version of sciserver. I just built the sciserver in the build directory using the command make -s sciserver_testapp_freertos CORE=mcu1_0 BUILD_PROFILE=debug.

    Based on your suggestion, I attempted to build the release version of sciserver using the command make -s sciserver_testapp_freertos CORE=mcu1_0 BUILD_PROFILE=release.I tried the following several combinations, but all failed. The program will still be blocked at sciclient_init.

    sciserver ipc_test_mcu1_1 ipc_test_mcu2_0 comment
    debug debug debug sciclient_init is blocked
    release release release sciclient_init is blocked
    prebuilt release release sciclient_init is blocked

    The result of the experiment confused me very much.  Your answer mentioned that when the sciserver is built in the release mode, you can successfully execute my program.

    Could you package your test as an example? In this way, perhaps I can better locate the problem.

    I also encountered an issue during the test. When I run ipc_rtos_sanity_test(<PDK_PATH>/packages/ti/drv/ipc/examples/rtos/ipc_rtos_sanity_test) on mcu1_0 (after commenting out the ipc_echo_test function and retaining only the basic initialization function, while building the test in debug mode), my application (also built in debug mode) no longer blocks at sciclient_init.

    Therefore, I suspect that the reason for the program blocking at sciclient_init is not related to whether the sciserver is built in release mode. I believe there may be some implicit configurations associated with using IPCLLD that are not mentioned in the documentation.

  • Hi,

    Could you package your test as an example? In this way, perhaps I can better locate the problem.

    When I tried running your example, program load is failing due to TCMA memory access. Able to execute your application by moving the MCU0_R5F_TCMA content to MCU0_R5F_TCMB0 in linker command file. I've included the test binaries built in our environment and log for your reference. Can you please try running them with your setup and share your observations.

    IPC Test Binaries and Logs.zip

    Regards,

    Karthik

  • Hi,

    I have run the binaries you provided on my J721E, unfortunately, they did not work successfully. The programs running on mcu1_1 and mcu2_0 are still blocked at sciclient_init.

  • Hi,

    I have run the binaries you provided on my J721E, unfortunately, they did not work successfully. The programs running on mcu1_1 and mcu2_0 are still blocked at sciclient_init.

    Have you made any changes to the launch.js file? If so, could you share with me the file? and could you tell me which SDK and CCS version you are using?

    Regards,

    Karthik

  • Hi,

    I only change the pdkPath and  loadSciserverFlag in the launch.js file.

    The version of SDK I'm using is PROCESSOR-SDK-RTOS-J721E —10.00.00.05.

    The version of CCS I'm using is CCS12.8.1.00005.

    Could you please tell me which SDK and CCS version you are using? Perhaps I need to reconfigure my development environment.

    The following is the code of my launch.js file.

    /*
     * Copyright (c) 2018-2019, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    //
    //File Name: launch_j721e.js
    //Description:
    //   Launch the DMSC firmware and board configuration from R5F.
    //
    //Usage:
    //
    //From CCS Scripting console
    //  1. loadJSFile "C:\\ti\\launch_j721e.js"
    //
    //Note:
    //  1. Search for "edit this" to look at changes that need to be edited
    //     for your usage.
    //
    
    
    //<!!!!!! EDIT THIS !!!!!>
    // Set this to 1, if using 'FreeRTOS'
    isFreertos = 1;  
    // Set this to 1, if using 'SafeRTOS'
    isSafertos = 0;  
    
    //PDK path. Edit this
    //pdkPath = "/ti/j7presi/workarea/pdk";
    pdkPath = "/home/user/Downloads/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27";
    //path to board config elf
    pathSciclient = pdkPath+"/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/"
    ccs_init_elf_file = pathSciclient+"sciclient_ccs_init_mcu1_0_release.xer5f";
    
    // Set this to 1, to clear 'Secure Claim' Bit in CLEC register
    clearCLECSecureClaimFlag = 1;
    
    loadSciserverFlag = 0;
    //loadSciserverFlag = 1;
    if(isFreertos == 1)
    {
        //Path to FreeRTOS sciserver
        sciserver_elf_file = pathSciclient+"sciserver_testapp_freertos_mcu1_0_release.xer5f";
    }
    else if(isSafertos == 1)
    {
        //Path to SafeRTOS sciserver
        sciserver_elf_file = pathSciclient+"sciserver_testapp_safertos_mcu1_0_release.xer5f";
    }
    
    //path to sysfw bin
    sysfw_bin = pdkPath+"/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j721e-gp.bin"
    
    //<!!!!!! EDIT THIS !!!!!>
    
    // Import the DSS packages into our namespace to save on typing
    importPackage(Packages.com.ti.debug.engine.scripting)
    importPackage(Packages.com.ti.ccstudio.scripting.environment)
    importPackage(Packages.java.lang);
    importPackage(Packages.java.io);
    
    function updateScriptVars()
    {
        //Open a debug session
        dsMCU1_0 = debugServer.openSession( ".*MCU_Cortex_R5_0" );
        dsDMSC_0 = debugServer.openSession( ".*DMSC_Cortex_M3_0" );
    }
    
    function printVars()
    {
        updateScriptVars();
    }
    
    function connectTargets()
    {
        /* Set timeout of 20 seconds */
        script.setScriptTimeout(200000);
        updateScriptVars();
        sysResetVar=dsDMSC_0.target.getResetType(1);
        sysResetVar.issueReset();
        print("Connecting to DMSC_Cortex_M3_0!");
        // Connect targets
        dsDMSC_0.target.connect();
        print("Fill R5F ATCM memory...");
        dsDMSC_0.memory.fill(0x61000000, 0, 0x8000, 0);
        print("Writing While(1) for R5F")
        dsDMSC_0.memory.writeWord(0, 0x61000000, 0xE59FF004); /* ldr        pc, [pc, #4] */
        dsDMSC_0.memory.writeWord(0, 0x61000004, 0x38);       /* Address 0x38 */
        dsDMSC_0.memory.writeWord(0, 0x61000038, 0xEAFFFFFE) /* b          #0x38 */
        print("Loading DMSC Firmware ... " + sysfw_bin);
        // Load the DMSC firmware
        dsDMSC_0.memory.loadRaw(0, 0x40000, sysfw_bin, 32, false);
        print("DMSC Firmware Load Done...");
        // Set Stack pointer and Program Counter
        stackPointer = dsDMSC_0.memory.readWord(0, 0x40000);
        progCounter = dsDMSC_0.memory.readWord(0, 0x40004);
        dsDMSC_0.memory.writeRegister("SP", stackPointer);
        dsDMSC_0.memory.writeRegister("PC", progCounter);
        print( "DMSC Firmware run starting now...");
        // Run the DMSC firmware
        dsDMSC_0.target.runAsynch();
        // Run the DDR Configuration
        print("Running the DDR configuration... Wait till it completes!");
        dsDMSC_0.target.halt();
        dsDMSC_0.expression.evaluate("J7ES_LPDDR4_Config_Late()");
        dsDMSC_0.target.runAsynch();
    
        print("Connecting to MCU Cortex_R5_0!");
    
        // Connect the MCU R5F
        dsMCU1_0.target.connect();
        // This is done to support other boot modes. OSPI is the most stable.
        // MMC is not always stable.
        bootMode = dsMCU1_0.memory.readWord(0, 0x43000030) & 0xF8;
        print (" WKUP Boot Mode is " + bootMode);
        mainBootMode = dsMCU1_0.memory.readWord(0, 0x100030) & 0xFF;
        print (" Main Boot Mode is " + mainBootMode);
        if ((bootMode != 0x38) || (mainBootMode != 0x11))
        {
            print("Disable MCU Timer for ROM clean up");
            dsMCU1_0.memory.writeWord(0, 0x40400010, 0x1); /* Write reset to MCU Timer 0. Left running by ROM */
            dsMCU1_0.memory.writeWord(0, 0x40F80430, 0xFFFFFFFF); /* Clear Pending Interrupts */
            dsMCU1_0.memory.writeWord(0, 0x40F80018, 0x0); /* Clear Pending Interrupts */
            // Reset the R5F to be in clean state.
            dsMCU1_0.target.reset();
            // Load the board configuration init file.
            dsMCU1_0.expression.evaluate('GEL_Load("'+ ccs_init_elf_file +'")');
            // Run Asynchronously
            dsMCU1_0.target.runAsynch();
            print ("Running Async");
            // Halt the R5F and re-run.
            dsMCU1_0.target.halt();
        }
        // Reset the R5F to be in clean state.
        dsMCU1_0.target.reset();
        print("Running the board configuration initialization from R5!");
        // Load the board configuration init file.
        dsMCU1_0.memory.loadProgram(ccs_init_elf_file);
        // Halt the R5F and re-run.
        dsMCU1_0.target.halt();
        // Run Synchronously for the executable to finish
        dsMCU1_0.target.run();
    }
    
    function disconnectTargets()
    {
        updateScriptVars();
        // Reset MCU1_0
        dsMCU1_0.target.reset();
        // Disconnect targets
        dsDMSC_0.target.disconnect();
    }
    
    function sampleDDRCheck ()
    {
        print("Running DDR Memory Checks....");
        dsMCU1_0.memory.fill (0x80000000, 0, 1024, 0xA5A5A5A5);
        ar = dsMCU1_0.memory.readWord(0, 0x80000000, 1024);
        fail = 0
        for (i = 0; i < ar.length; i++) { 
                x = ar[i]; 
                if (x != 0xA5A5A5A5)
                {
                    fail = 1;
                }
            } 
        if (fail == 1)
        {
            print ("0x80000000: DDR memory sample check failed !!");
        }
        dsMCU1_0.memory.fill (0x81000000, 0, 1024, 0x5A5A5A5A);
        ar = dsMCU1_0.memory.readWord(0, 0x81000000, 1024);
        fail = 0
        for (i = 0; i < ar.length; i++) { 
                x = ar[i]; 
                if (x != 0x5a5a5a5a)
                {
                    fail = 1;
                }
            } 
        if (fail == 1)
        {
            print ("0x81000000: DDR memory sample check failed !!");
        }
    }
    
    function loadSciserver()
    {
        updateScriptVars();
        print("######################################################################################");
        print("Loading Sciserver Application on MCU1_0. This will service RM/PM messages");
        print("If you do not want this to be loaded update the launch script to make loadSciserverFlag = 0");
        print("If you want to load and run other cores, please run the MCU1_0 core after Sciserver is loaded. ");
        print("######################################################################################");
        dsMCU1_0.expression.evaluate('GEL_Load("'+ sciserver_elf_file +'")');
    }
    
    function clearCLECSecureClaim()
    {
        dsC7X1_0 = debugServer.openSession( ".*C71X_0" );
    
        dsC7X1_0.target.connect();
    
        c7x_binary = pdkPath+"/packages/ti/drv/sciclient/tools/clearClecSecureClaim/sciclient_clear_clec_secure_claim_c7x_1_release.xe71";
    
        dsC7X1_0.memory.loadProgram(c7x_binary);
        dsC7X1_0.target.runAsynch();
    
        // Halt and re-run since the startup code image doesn't have a main function.
        dsC7X1_0.target.halt();
        dsC7X1_0.target.runAsynch();
    
        dsC7X1_0.target.disconnect();
    }
    
    function doEverything()
    {
        printVars();
        connectTargets();
        disconnectTargets();
        sampleDDRCheck ();
        if (clearCLECSecureClaimFlag == 1)
        {
            print("Clearing CLEC Secure Claim...");
            clearCLECSecureClaim();
        }
        if (loadSciserverFlag == 1)
        {
            loadSciserver();
        }
        print("Happy Debugging!!");
    }
    
    var ds;
    var debugServer;
    var script;
    
    // Check to see if running from within CCSv4 Scripting Console
    var withinCCS = (ds !== undefined);
    
    // Create scripting environment and get debug server if running standalone
    if (!withinCCS)
    {
        // Import the DSS packages into our namespace to save on typing
        importPackage(Packages.com.ti.debug.engine.scripting);
        importPackage(Packages.com.ti.ccstudio.scripting.environment);
        importPackage(Packages.java.lang);
    
        // Create our scripting environment object - which is the main entry point into any script and
        // the factory for creating other Scriptable ervers and Sessions
        script = ScriptingEnvironment.instance();
    
        // Get the Debug Server and start a Debug Session
        debugServer = script.getServer("DebugServer.1");
    }
    else // otherwise leverage existing scripting environment and debug server
    {
        debugServer = ds;
        script = env;
    }
    
    doEverything();
    

  • Hi,

    Would you please send your launch.js and GEL file CCS console logs?

    Could you please tell me which SDK and CCS version you are using?

    I am using ti-processor-sdk-rtos-j721e-evm-11_00_00_06, and Code Composer Studio version 12.8.

    Regards,

    Karthik

  • Hi,

    I have rebuilt my development environment using ti-processor-sdk-rtos-j721e-evm-11_00_00_06. Unfortunately, the programs running on mcu1_1 and mcu2_0 are still blocked at sciclient_init.

    Would you please send your launch.js and GEL file CCS console logs?

    I have packed and uploaded the files you need.

    j721e_logs_gel_launch.zip

  • Hi,

    Can you check by setting "loadSciserverFlag", SciServer should run on MCU1_0 core in order to service any of client core requests.

    Best Regards,
    Sudheer

  • Hi, 

    I have tested it, and the results are as follows, where prebuilt means loadSciserverFlag=1 and directly uses the compiled sciserver program in pdk.

    Based on your suggestion, I attempted to build the release version of sciserver using the command make -s sciserver_testapp_freertos CORE=mcu1_0 BUILD_PROFILE=release.I tried the following several combinations, but all failed. The program will still be blocked at sciclient_init.

    sciserver ipc_test_mcu1_1 ipc_test_mcu2_0 comment
    debug debug debug sciclient_init is blocked
    release release release sciclient_init is blocked
    prebuilt release release sciclient_init is blocked

    The result of the experiment confused me very much.  Your answer mentioned that when the sciserver is built in the release mode, you can successfully execute my program.

  • Hi,

    Could you please confirm whether you received logs from the MCU1_0 core? If yes,can you share the logs with me? Also, could you let me know whether you are using a TI EVM or a Custom Device?

    Regards,

    Karthik