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No Access to USBTLL registers and EHCI controller is always in reset.

Ludwig Zenz
Intellectual 820 points
Other Parts Discussed in Thread: AM3517, SYSCONFIG

Hello,

I want to use the USB Host High Speed Port on the am3517 in u-boot. We have connected a SMSC USB3320 PHY to the hsusb1_xx pins.

As there is no EHCI support in the u-boot code for the am3517evm from logicPD, i integrated the code from beagleboard u-boot.

This is what the code does in ehci_hcd_init:

- putting the PHY in reset

- Enable USBHOST_L3_ICLK (USBHOST_MICLK)

- Enable USBHOST_48M_FCLK (USBHOST_FCLK1) and USBHOST_120M_FCLK (USBHOST_FCLK2)

- Enable USBTTL_ICLK

- Enable USBTTL_FCLK

- The Code from beagleboard wants to make a softreset of TLL here, but i have no access to the USBTLL subsystem at this point. It seems this Subsystem is still deactivated.

 

Can someone give same hints what i am missing?

Is there a Application Note or something similar for this? The reference manual did not really help.

 

An additional information I can give, it seems the ehci controller is always in reset mode. The UHH_SYSSTATUS.EHCI_RESETDONE bit is always 0 (reset is ongoing).

 

Thank You!

 

 

 

  • 0
    Intellectual 820 points

    Has someone a patch for u-boot to work with the USB Host HS port?

    I am not really sure if some points from the chip errata making the problems. Can someone give some additional information?

     

    Thank You!

     

  • 0
    Prodigy 10 points

    Well,  the same problem happens,

    /* perform TLL soft reset, and wait until reset is complete */
     writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
      OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
     /* Wait for TLL reset to complete */
     while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
       & OMAP_USBTLL_SYSSTATUS_RESETDONE));

    It can not run out of while loop,  the UHH_SYSSTATUS.EHCI_RESETDONE bit is always 0 (reset is ongoing), what happens?

  • 0 in reply to Joe Zhou
    Intellectual 820 points

    Hello Joe Zhou,

    maybe this helps you:

    I configured the DPLL5 clock. This is necessary for the 120M_FCLK.

    Following registers you have to set: clksel4_pll, clken2_pll

    regards,

    Ludwig