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TDA4AL-Q1: DDR Configuration Checking For MT53E256M32D1 LPDDR4

Part Number: TDA4AL-Q1
Other Parts Discussed in Thread: TDA4VL, SYSCONFIG

Tool/software:

Hi, Dear Expert

This is an extension discussion from this thread,

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1498739/tda4al-q1-failed-to-start-ccs-after-loadjsfile-launch-js-stop-at-j721s2-running-the-ddr-configuration-wait-till-it-completes/5805207#5805207

Because customer try to launch CCS debug with customized board for 1GB LPDDR4, and I saw this error message

so I suspect it should be DDR initialize problems, post this thread for DDR setting double checking.

721S2 Running the DDR configuration... Wait till it completes!
Error evaluating "J7_LPDDR4_Config_Late()": Target failed to read 0x80114080
at (*((unsigned int*) (0x80000000U+fsp_clkchng_req_addr))&0x80) [J7_DDR_Config.gel:3337]
at DDRSS_LPDDR4_Ack_Freq_Upd_Req(ddrss_num) [J7_DDR_Config.gel:3413]
at J7_LPDDR4_Config_Single(0) [J7_DDR_Config.gel:3699]
at J7_LPDDR4_Config() [J7_DDR_Config.gel:3734]
at J7_LPDDR4_Config_Late() (C:\src\0506\launch.js#130)

(1) Pls check basic setting, is it correct?

(2) plc check Config A, System Configuration, is it correct?

(3) Config B, Memory Burst Configuration, is it correct?

(4) DRAM Timing A) Latency Parameters at Operating Frequency, is it correct?

DDR sys configure as attachment

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/tda4al_5F00_1g_5F00_ddr.syscfg

Thank You.

Gibbs

  • 1. I have changed 
    C:\ti\ccs1281\ccs\ccs_base\emulation\gel\J721S2_TDA4VL\J7AEP_DDR_SI\J7_DDR_Config.gel

    , J721S2-DDR-EVM-LP4.gel based on sysconfig

    2. Based on sysconfig j721s2_board_ddrRegInit.h      I have recomplied to generated sciclient_ccs_init_mcu1_0_release.xer5f

    cd ~/project/EGE/EGE-0512/rtos-build/pdk_j721s2_10_01_00_25/packages/ti/drv/sciclient
    export PATH=$PATH:/opt/ti/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin
    ln -s /opt/ti/ti-cgt-armllvm_3.2.2.LTS ~/project/EGE/EGE-0512/rtos-build/ti-cgt-armllvm_3.2.2.LTS
    ./tools/boardcfg_update.sh j721s2_evm --boardcfg=./soc/V4/sciclient_defaultBoardcfg_rm.c

  • Gibbs,

    Although the error message is occurring inside the DDR GEL function, the error message doesn't have anything to do with the register settings.

    Specifically, the error message is saying it cannot read address 0x80114080. If you look more closely at the next line, an offset of 0x80000000 was added (to compensate for the GEL M4 RAT configuration), so the address it is actually trying to read is 0x00114080, or the CTRL_MMR_DDR4_FSP_CLKCHNG_REQ0 register which is a part of the control MMR0 register space.

    I am not familiar with the launch javascript procedure which is being used, but maybe it does not setup the M4 RAT the same way as the GELs, and thus you are not reading the correct address to access the CTRL_MMR_DDR4_FSP_CLKCHNG_REQ0 register.

    I'll re-assign the ticket to see if someone from the software team can comment.

    Error evaluating "J7_LPDDR4_Config_Late()": Target failed to read 0x80114080
    at (*((unsigned int*) (0x80000000U+fsp_clkchng_req_addr))&0x80) [J7_DDR_Config.gel:3337]
    at DDRSS_LPDDR4_Ack_Freq_Upd_Req(ddrss_num) [J7_DDR_Config.gel:3413]
    at J7_LPDDR4_Config_Single(0) [J7_DDR_Config.gel:3699]
    at J7_LPDDR4_Config() [J7_DDR_Config.gel:3734]
    at J7_LPDDR4_Config_Late() (C:\src\0506\launch.js#130)

    Regards,
    Kevin

  • Hi Gibbs,

    so I suspect it should be DDR initialize problems, post this thread for DDR setting double checking.

    Please try loading the J7_LPDDR4_Config() file from M4F_0 core rather than the launch.js file and directly access the DDR memory from Memory Browser . This will helps to  determine whether your configuration is correct. please let us know if you are able to access the DDR memory.

    Please refer to the screenshot and flow diagram that are given below to configure the gel from the M4F_0 core.

    Launch Target configuration (J721s2.ccxml) ->  connect CORTEX_M4_0 Core -> Open Scripts -> J7 DDR Memory Config -> Load J7_LPDDR4_Config -> Connect MCU_Cortex_R5_0 Core -> Open Memory Browser -> write the value into DDR

    DDR_Config_Issue.zip

    Regards,

    Karthik