TDA4AL-Q1: GPIO_socConfigIntrPath init fail in SDK0806

Xingyu Zhu

Part Number: TDA4AL-Q1

Tool/software:

Hi expert,

Our customer is working on the interrupt function of pin EXTINTN with SDK0806 on MCU2_0 of TDA4AL. They found gpio API: GPIO_socConfigIntrPath in the default PDK init will fail. By searching on E2E, we found there is an existing issue on SDK0806: https://sir.ext.ti.com/jira/browse/EXT_EP-10914, and this issue will be fixed in SDK0901. Given our customer don't have plan to upgrade SDK, need your help to provide a patch working on SDK0806. Thanks

Best Regards,

Xingyu Zhu

3 months ago

0 Neehar Sawant 3 months ago

TI__Mastermind 19370 points

Hi Xingyu,

Who is the customer?

Xingyu Zhu said:
They found gpio API: GPIO_socConfigIntrPath in the default PDK init will fail.

Additionally, what error is returned by the function?

Thanks,

Neehar

0 zhao li 3 months ago in reply to Neehar Sawant

Prodigy 180 points

hi Neehar，
Sciclient_rmIrqSet() return -1 with the following parameters:

rmIrqReq.src_id           = TISCI_DEV_GPIO0;
rmIrqReq.src_index        = 0;  
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

rmIrqReq.dst_id       = TISCI_DEV_R5FSS0_CORE0;
rmIrqReq.dst_host_irq = 396;

The code execution path is Sciclient_rmIrqSet() -> Sciclient_rmProgramInterruptRoute() -> Sciclient_rmIrqFindRoute() , return CSL_EFAIL with search_depth = 3.

I am using mcu2_0.SDK and PDK version is ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/pdk_j721s2_08_06_01_03.

TI experts Parth Nagpal mentioned "There has been a known issue with main domain GPIO interrupts which has been fixed in SDK 9.1.

https://sir.ext.ti.com/jira/browse/EXT_EP-10914 " in the following link:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1299569/tda4vm-configuration-for-gpio-interrupt/4933949?tisearch=e2e-sitesearch&keymatch=PDK%2520GPIO#4933949

Thanks
Zhao Li

0 zhao li 3 months ago in reply to zhao li

Prodigy 180 points

Hi Neehar,
Here is the pinmux config:

static pinmuxPerCfg_t gMain_gpio0PinCfg[] =
{
    /* PIN_EXTINTN -> AG24 */
    {
        PIN_EXTINTN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE | PIN_OUTPUT_DISABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

gpio config code:

/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] =
{
    /* Input pin */
    GPIO_DEVICE_CONFIG(0, 0) | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,    /*AG24 PIN_EXTINTn GPIO0_0*/
};

void AppGpioCallbackFxn(void)
{
    appLogPrintf("signal changed\n");
}

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] =
{
   NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config =
{
    gpioPinConfigs,
    gpioCallbackFunctions,
    sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
    sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
    0x8U
#else
#if defined(BUILD_C7X)
    0x01U
#else
    0x20U
#endif
#endif
};


int32_t appGPIOInit()
{
    GPIO_v0_HwAttrs gpio_cfg;

    /* Get the default init configurations */
    GPIO_socGetInitCfg(0, &gpio_cfg);
    gpio_cfg.baseAddr = CSL_GPIO0_BASE;
    GPIO_socSetInitCfg(0, &gpio_cfg);

    /* Initializes the gpio */
    GPIO_init();

    /* Set the callback function */
    GPIO_setCallback(0, AppGpioCallbackFxn);

    /* Enable GPIO interrupt on the specific gpio pin */
    GPIO_enableInt(0);

    return 0;
}

The output log of MCU2_0 is as follows:

[MCU2_0]      3.238168 s: GPIO_setConfig_v0:502 gpio port 0 pin 0 direction 1
[MCU2_0]      3.238233 s: GPIO_setConfig_v0:514 gpioPortIntIdx 0 portHwiCreatedBitMask 0x0 gpioPortIntBitMask 0x1
[MCU2_0]      3.238309 s: GPIO_socConfigIntrPath:467 portNum 0 pinNum 0 setIntrPath 1 baseAddr 0x600000
[MCU2_0]      3.238362 s: GPIO_socGetCoreSciId:690 BUILD_MCU devId 279
[MCU2_0]      3.238424 s: GPIO_socConfigIntrPath:539 ir_id 148 src_id 111 src_index 0 dst_id 279
[MCU2_0]      3.238544 s: GPIO_socConfigIntrPath:544 retVal 0 irq_range_start 396 irq_range_num 4
[MCU2_0]      3.238595 s: GPIO_socConfigIntrPath:566 retVal 0
[MCU2_0]      3.238699 s: Sciclient_rmIrqFindRoute:1975 retVal -1 search_depth 3 Sciclient_rmPsGetMaxPsp 3
[MCU2_0]      3.238760 s: Sciclient_rmProgramInterruptRoute:905 d_irq is 0x18c retVal -1
[MCU2_0]      3.238809 s: Sciclient_rmProgramInterruptRoute:945 retVal -1
[MCU2_0]      3.238852 s: GPIO_socConfigIntrPath:592 retVal -1
[MCU2_0]      3.238900 s: GPIO_setConfig_v0:552 Configure SOC interrupt path ret_socIntrPath -1
[MCU2_0]      3.238954 s: GPIO_setConfig_v0:562 eventId 0 intNum 396
[MCU2_0]      3.238995 s: GPIO_setConfig_v0:569 R5F  OSAL_ARM_GIC_TRIG_TYPE_EDGE
[MCU2_0]      3.239040 s: GPIO_setConfig_v0:580 error constructing the Hwi for GPIO Port

Thanks
Zhao Li

0 Neehar Sawant 3 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

Thanks for this information. I will look into this further and get back to you.

Thanks,

Neehar

0 zhao li 3 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neehar,
Is there any update on this issue?
Thanks
Zhao Li

0 Neehar Sawant 3 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

Do you have issues configuring interrupt path for all GPIO on any core? Or is the issue solely on GPIO0_0 on MCU2_0?

Thanks,

Neehar

0 zhao li 3 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neehar,
I tried GPIO0_17、GPIO0_28 and GPIO0_34, all failed to configure interrupt path. Bye the way, GPIO_read() can get correct 0,1,1 。

gpio config code:

/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] =
{
    /* Input pin */
    GPIO_DEVICE_CONFIG(0, 17) | GPIO_CFG_INPUT  | GPIO_CFG_IN_INT_LOW,   /*E20 PIN_MCU_OSPI0_LBCLKO GPIO0_17*/
    /* Input pin */
    GPIO_DEVICE_CONFIG(0, 28) | GPIO_CFG_INPUT  | GPIO_CFG_IN_INT_HIGH,    /*G17 PIN_MCU_OSPI0_CSN1 GPIO0_28*/
    /* Input pin */
    GPIO_DEVICE_CONFIG(0, 34) | GPIO_CFG_INPUT  | GPIO_CFG_IN_INT_HIGH,     /*G17 PIN_MCU_OSPI1_D0 GPIO0_34*/
};

void AppGpioLevelHighCallbackFxn(void)
{
    appLogPrintf("gpio level high int\n");
}

void AppGpioLevelLowCallbackFxn(void)
{
    appLogPrintf("gpio level low int\n");
}

int32_t appGPIOInit()
{
    GPIO_v0_HwAttrs gpio_cfg;

    /* Get the default SPI init configurations */
    GPIO_socGetInitCfg(0, &gpio_cfg);
    gpio_cfg.baseAddr = CSL_WKUP_GPIO0_BASE;
        (gpio_cfg.intCfg[0]).intcMuxNum = INVALID_INTC_MUX_NUM;
        (gpio_cfg.intCfg[0]).intcMuxInEvent = 0;
        (gpio_cfg.intCfg[0]).intcMuxOutEvent = 0;
    GPIO_socSetInitCfg(0, &gpio_cfg);

    /* Initializes the gpio */
    GPIO_init();

    /* Set the callback function */
    GPIO_setCallback(GPIO_HW_ID_1, AppGpioLevelLowCallbackFxn);
    GPIO_setCallback(GPIO_HW_ID_2, AppGpioLevelHighCallbackFxn);
    GPIO_setCallback(GPIO_HW_ID_3, AppGpioLevelHighCallbackFxn);

    /* Enable GPIO interrupt on the specific gpio pin */
    GPIO_enableInt(GPIO_HW_ID_1);
    GPIO_enableInt(GPIO_HW_ID_2);
    GPIO_enableInt(GPIO_HW_ID_3);

    return 0;
}

The output log of MCU2_0 is as follows:

[MCU2_0]      3.583947 s: GPIO_setConfig_v0:502 gpio port 0 pin 17 direction 1
[MCU2_0]      3.584014 s: GPIO_setConfig_v0:514 gpioPortIntIdx 0 portHwiCreatedBitMask 0x0 gpioPortIntBitMask 0x1
[MCU2_0]      3.584091 s: GPIO_socConfigIntrPath:467 portNum 0 pinNum 17 setIntrPath 1 baseAddr 0x42110000
[MCU2_0]      3.584145 s: GPIO_socGetCoreSciId:689 BUILD_MCU devId 279
[MCU2_0]      3.584206 s: GPIO_socConfigIntrPath:539 ir_id 125 src_id 115 src_index 1 dst_id 279
[MCU2_0]      3.584898 s: GPIO_socConfigIntrPath:544 retVal 0 irq_range_start 500 irq_range_num 2
[MCU2_0]      3.584953 s: GPIO_socConfigIntrPath:565 retVal 0
[MCU2_0]      3.585052 s: Sciclient_rmIrqFindRoute:1975 retVal -1 search_depth 3 Sciclient_rmPsGetMaxPsp() 3
[MCU2_0]      3.585117 s: Sciclient_rmProgramInterruptRoute:905 d_irq is 0x1f5 retVal -1
[MCU2_0]      3.585166 s: Sciclient_rmProgramInterruptRoute:945 retVal -1
[MCU2_0]      3.585209 s: GPIO_socConfigIntrPath:591 retVal -1
[MCU2_0]      3.585257 s: GPIO_setConfig_v0:552 Configure SOC interrupt path ret_socIntrPath -1
[MCU2_0]      3.585311 s: GPIO_setConfig_v0:562 eventId 0 intNum 501
[MCU2_0]      3.585351 s: GPIO_setConfig_v0:569 R5F  OSAL_ARM_GIC_TRIG_TYPE_EDGE
[MCU2_0]      3.585397 s: GPIO_setConfig_v0:580 error constructing the Hwi for GPIO Port

[MCU2_0]      3.585456 s: GPIO_setConfig_v0:502 gpio port 0 pin 28 direction 1
[MCU2_0]      3.585518 s: GPIO_setConfig_v0:514 gpioPortIntIdx 0 portHwiCreatedBitMask 0x0 gpioPortIntBitMask 0x1
[MCU2_0]      3.585593 s: GPIO_socConfigIntrPath:467 portNum 0 pinNum 28 setIntrPath 1 baseAddr 0x42110000
[MCU2_0]      3.585644 s: GPIO_socGetCoreSciId:689 BUILD_MCU devId 279
[MCU2_0]      3.585705 s: GPIO_socConfigIntrPath:539 ir_id 125 src_id 115 src_index 1 dst_id 279
[MCU2_0]      3.585825 s: GPIO_socConfigIntrPath:544 retVal 0 irq_range_start 500 irq_range_num 2
[MCU2_0]      3.585876 s: GPIO_socConfigIntrPath:565 retVal 0
[MCU2_0]      3.585964 s: Sciclient_rmIrqFindRoute:1975 retVal -1 search_depth 3 Sciclient_rmPsGetMaxPsp() 3
[MCU2_0]      3.586028 s: Sciclient_rmProgramInterruptRoute:905 d_irq is 0x1f5 retVal -1
[MCU2_0]      3.586077 s: Sciclient_rmProgramInterruptRoute:945 retVal -1
[MCU2_0]      3.586120 s: GPIO_socConfigIntrPath:591 retVal -1
[MCU2_0]      3.586167 s: GPIO_setConfig_v0:552 Configure SOC interrupt path ret_socIntrPath -1
[MCU2_0]      3.586220 s: GPIO_setConfig_v0:562 eventId 0 intNum 501
[MCU2_0]      3.586262 s: GPIO_setConfig_v0:569 R5F  OSAL_ARM_GIC_TRIG_TYPE_EDGE
[MCU2_0]      3.586307 s: GPIO_setConfig_v0:580 error constructing the Hwi for GPIO Port

[MCU2_0]      3.586366 s: GPIO_setConfig_v0:502 gpio port 0 pin 34 direction 1
[MCU2_0]      3.586428 s: GPIO_setConfig_v0:514 gpioPortIntIdx 0 portHwiCreatedBitMask 0x0 gpioPortIntBitMask 0x1
[MCU2_0]      3.586501 s: GPIO_socConfigIntrPath:467 portNum 0 pinNum 34 setIntrPath 1 baseAddr 0x42110000
[MCU2_0]      3.586553 s: GPIO_socGetCoreSciId:689 BUILD_MCU devId 279
[MCU2_0]      3.586613 s: GPIO_socConfigIntrPath:539 ir_id 125 src_id 115 src_index 2 dst_id 279
[MCU2_0]      3.586711 s: GPIO_socConfigIntrPath:544 retVal 0 irq_range_start 500 irq_range_num 2
[MCU2_0]      3.586760 s: GPIO_socConfigIntrPath:565 retVal 0
[MCU2_0]      3.586836 s: Sciclient_rmIrqFindRoute:1975 retVal -1 search_depth 3 Sciclient_rmPsGetMaxPsp() 3
[MCU2_0]      3.586898 s: Sciclient_rmProgramInterruptRoute:905 d_irq is 0x1f6 retVal -1
[MCU2_0]      3.586951 s: Sciclient_rmProgramInterruptRoute:945 retVal -1
[MCU2_0]      3.586995 s: GPIO_socConfigIntrPath:591 retVal -1
[MCU2_0]      3.587041 s: GPIO_setConfig_v0:552 Configure SOC interrupt path ret_socIntrPath -1
[MCU2_0]      3.587094 s: GPIO_setConfig_v0:562 eventId 0 intNum 502
[MCU2_0]      3.587134 s: GPIO_setConfig_v0:569 R5F  OSAL_ARM_GIC_TRIG_TYPE_EDGE
[MCU2_0]      3.587181 s: GPIO_setConfig_v0:580 error constructing the Hwi for GPIO Port

Thanks
Zhao Li

0 Neehar Sawant 3 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi,

Do you have the same issue on any other cores other than MCU2_0?

Thanks for the detailed logs, I am going through it deeper.

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi,
I'm trying to run the gpio code in userspace of A core, but I encountered a linking error during compilation “undefined reference to `GPIO_socSetInitCfg'”。
Maybe there is a known issue in sdk earlier than 9.1， refer to the following two links:
1. TI experts Parth Nagpal mentioned "There has been a known issue with main domain GPIO interrupts which has been fixed in SDK 9.1.”in the following link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1299569/tda4vm-configuration-for-gpio-interrupt/4933949?tisearch=e2e-sitesearch&keymatch=PDK%2520GPIO#4933949
2. TI jira https://sir.ext.ti.com/jira/browse/EXT_EP-10914 " --

Main Domain GPIO does not service interrupts

Fix In Release:
PROCESSOR_SDK_09.01.00

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

I am looking into it and will get back to you in a couple days.

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neehar,
I tried GPIO0_0 in A core， after manually changing the direction of the GPIO to input, the interrupt can be triggered.

Here is the test code

dts：
 main_gpio_pins_default: main-gpio-pins-default {
	pinctrl-single,pins = <
		J721S2_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
	>;
 };
 
 fsync-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
 

interrupt code：
static inline irqreturn_t sync_handler(int irq, void *id)
{
    struct timespec64 ts;
    ktime_get_ts64(&ts);
    pr_info("ktime_get_ts64(): %lld.%09ld\n", (long long)ts.tv_sec, ts.tv_nsec);
    return IRQ_HANDLED;
}

static int gpio_irq_init(struct device_node *node)
{
	int ret;
    int fsync_irq;
	int fsync_gpio;
	
    fsync_gpio = of_get_named_gpio(node, "fsync-gpios", 0);

    if (!gpio_is_valid(fsync_gpio))
        return -EINVAL;

    if (gpio_request(fsync_gpio, "gpio_label") < 0)
    {
        pr_err("Fail to request GPIO %d\n", fsync_gpio);
        return -EINVAL;
    }
    
    gpio_direction_input(fsync_gpio);

	fsync_irq = gpio_to_irq(fsync_gpio);
    ret = request_irq(fsync_irq, sync_camera_handler, IRQF_TRIGGER_RISING, "GPIO_FSYNC", NULL); 
    if (ret < 0)
    {
        pr_err("request fsync irq error ret:%d\n", ret);
        gpio_free(fsync_gpio);
        return -EINVAL;
    }

    pr_info("Success register fsync irq %d\n", fsync_irq);
    return 0;
}

There is no interrupt when GPIO0_0 value changes from 0 to 1

root@imotion:/mnt# ./devmem2 0x00600020
/dev/mem opened.
Memory mapped at address 0xffffb51f3000.
Read at address  0x00600020 (0xffffb51f3020): 0x2A1C4EF4  ==> bit0 value 0

root@imotion:/mnt# ./devmem2 0x00600020
/dev/mem opened.
Memory mapped at address 0xffff87bdb000.
Read at address  0x00600020 (0xffff87bdb020): 0x2A1D4EF5  ==> bit0 value 1

root@imotion:/mnt# cat /proc/interrupts | grep GPIO
263:          0          0      GPIO   0 Edge    -davinci_gpio  GPIO_FSYNC ==>interrupt 0

After changing direction of GPIO0_0 from output to input, interrupt can be triggered

root@imotion:/mnt# ./devmem2 0x00600010
/dev/mem opened.
Memory mapped at address 0xffff9c797000.
Read at address  0x00600010 (0xffff9c797010): 0xFFFFFFFE  => bit 0 output
root@imotion:/mnt# ./devmem2 0x00600010 w 0xFFFFFFFF
/dev/mem opened.
Memory mapped at address 0xffff843e3000.
Read at address  0x00600010 (0xffff843e3010): 0xFFFFFFFE
Write at address 0x00600010 (0xffff843e3010): 0xFFFFFFFF, readback 0xFFFFFFFF => bit 0 input

root@imotion:/mnt# ./devmem2 0x00600020
/dev/mem opened.
Memory mapped at address 0xffffb51f3000.
Read at address  0x00600020 (0xffffb51f3020): 0x2A1C4EF4 => bit 0 value 0

root@imotion:/mnt# ./devmem2 0x00600020
/dev/mem opened.
Memory mapped at address 0xffff87bdb000.
Read at address  0x00600020 (0xffff87bdb020): 0x2A1D4EF5 => bit 0 value 1

root@imotion:/mnt# cat /proc/interrupts | grep GPIO
263:          1          0      GPIO   0 Edge    -davinci_gpio  GPIO_FSYNC  ==>interrupt triggered

The code gpio_direction_input(sync_gpio) has already set direction of GPIO0_0 to input, have no idea why it turns to be output.

[    1.623786]__davinci_direction offset 0x0 bank 0x0 mask 0x1 read-value 0xffffffff
[    1.632988]__davinci_direction offset 0x0 bank 0x0 mask 0x1 write-value 0xffffffff

Importantly, the interrupt can finally be triggered successfully in A core, not work in MCU2_0.

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

Have you made any changes to sciclient_defaultBoardcfg_rm.c?

This file can be found at: [PDK_INSTALL_PATH]/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm.c

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neehar,
I have checked the git repo， no change history about sciclient_defaultBoardcfg_rm.c, it's consistent with that in the original package ti-processor-sdk-rtos-j721s2-evm-08_06_01_03

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

zhao li said:
The output log of MCU2_0 is as follows:

The values for the sciclient call in this case are correct. I am looking deeper into why the sciclient calls are failing.

zhao li said:
The output log of MCU2_0 is as follows:

The values are correct for the sciclient call for all three WKUP_GPIO pins as well. However, there are only 2 interrupt lines allocated from WKUP_GPIOMUX_INTR. Therefore, you will not be able to register the interrupt for all three pins unless you allocate more lines to the core.

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neerhar,
Sorry, the information previously provided about the modification of the file sciclient_defaultBoardcfg_rm.c was incorrect. To allocate DMA resources to MCU2_1, our colleague modified this file in SBL.

diff --git a/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm.c b/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm.c
index 3f91d187c..fe5e4e35d 100755
--- a/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm.c
+++ b/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm.c
@@ -645,21 +645,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 4,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
             .start_resource = 416,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 2,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 417,
+            .start_resource = 420,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 2,
+            .num_resource = 1,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 419,
+            .start_resource = 420,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -909,15 +909,15 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 3,
+            .num_resource = 4,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
             .start_resource = 17,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 3,
+            .num_resource = 2,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
-            .start_resource = 20,
+            .start_resource = 21,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
@@ -1071,21 +1071,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 4,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
             .start_resource = 75,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 2,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 76,
+            .start_resource = 79,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 2,
+            .num_resource = 1,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 78,
+            .start_resource = 79,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -1629,21 +1629,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
             .start_resource = 57,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 58,
+            .start_resource = 60,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 59,
+            .start_resource = 60,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -1689,21 +1689,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
             .start_resource = 81,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 82,
+            .start_resource = 84,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
-            .start_resource = 83,
+            .start_resource = 84,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -1755,21 +1755,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
             .start_resource = 9,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
-            .start_resource = 10,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
-            .start_resource = 11,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -1815,21 +1815,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
             .start_resource = 33,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
-            .start_resource = 34,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
-            .start_resource = 35,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -2055,21 +2055,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
             .start_resource = 9,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 10,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 11,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -2115,21 +2115,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
             .start_resource = 33,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 34,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
-            .start_resource = 35,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -2193,21 +2193,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
             .start_resource = 9,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
-            .start_resource = 10,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
-            .start_resource = 11,
+            .start_resource = 12,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
@@ -2253,21 +2253,21 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 3,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
             .start_resource = 33,
             .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
-            .start_resource = 34,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
         },
         {
-            .num_resource = 1,
+            .num_resource = 0,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
-            .start_resource = 35,
+            .start_resource = 36,
             .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
         },
         {
diff --git a/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm_hex.h b/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm_hex.h
index caf767ce0..d9cdc2edf 100644
--- a/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm_hex.h
+++ b/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/soc/V4/sciclient_defaultBoardcfg_rm_hex.h
@@ -134,8 +134,8 @@
     0x40c20002U,     0x016e0003U,     0x40c20002U,     0x01700005U, \
     0x40c20016U,     0x0186000cU,     0x40c20006U,     0x018c000dU, \
     0x40c20004U,     0x01900015U,     0x40c20004U,     0x01940017U, \
-    0x40c2000cU,     0x01a00023U,     0x40c20001U,     0x01a10025U, \
-    0x40c20002U,     0x01a30028U,     0x40c20002U,     0x01a5002aU, \
+    0x40c2000cU,     0x01a00023U,     0x40c20004U,     0x01a40025U, \
+    0x40c20000U,     0x01a40028U,     0x40c20001U,     0x01a5002aU, \
     0x40c20002U,     0x00040080U,     0x40c30006U,     0x000a000cU, \
     0x40c30000U,     0x000a000dU,     0x40c30002U,     0x000c0015U, \
     0x40c30002U,     0x000e0017U,     0x40c30006U,     0x00140023U, \
@@ -156,8 +156,8 @@
     0x40ca0005U,     0x0007000cU,     0x40ca0001U,     0x0000000dU, \
     0x40cb0003U,     0x0003000cU,     0x40cb0002U,     0x0005000dU, \
     0x40cb0003U,     0x00080015U,     0x40cb0003U,     0x000b0017U, \
-    0x40cb0006U,     0x00110023U,     0x40cb0003U,     0x00140025U, \
-    0x40cb0003U,     0x00170028U,     0x40cb0003U,     0x001a002aU, \
+    0x40cb0006U,     0x00110023U,     0x40cb0004U,     0x00150025U, \
+    0x40cb0002U,     0x00170028U,     0x40cb0003U,     0x001a002aU, \
     0x40cb0001U,     0x001b0003U,     0x40cb0001U,     0x001c0005U, \
     0x40cb0004U,     0x00520080U,     0x41c00010U,     0x0062000cU, \
     0x41c00010U,     0x0072000dU,     0x41c0006eU,     0x00000080U, \
@@ -170,8 +170,8 @@
     0x41ca0002U,     0x001b0005U,     0x41ca0016U,     0x0031000cU, \
     0x41ca0006U,     0x0037000dU,     0x41ca0004U,     0x003b0015U, \
     0x41ca0004U,     0x003f0017U,     0x41ca000cU,     0x004b0023U, \
-    0x41ca0001U,     0x004c0025U,     0x41ca0002U,     0x004e0028U, \
-    0x41ca0002U,     0x0050002aU,     0x41ca0002U,     0x00020080U, \
+    0x41ca0004U,     0x004f0025U,     0x41ca0000U,     0x004f0028U, \
+    0x41ca0001U,     0x0050002aU,     0x41ca0002U,     0x00020080U, \
     0x41cb0001U,     0x0003000cU,     0x41cb0001U,     0x00000023U, \
     0x41cc0001U,     0x0001000cU,     0x41cc0001U,     0x00040023U, \
     0x41cd0006U,     0x000a000cU,     0x41cd0000U,     0x000a000dU, \
@@ -216,24 +216,24 @@
     0x4401000cU,     0x00e00005U,     0x4401001cU,     0x00320080U, \
     0x44020004U,     0x0036000cU,     0x44020000U,     0x0036000dU, \
     0x44020001U,     0x00370015U,     0x44020001U,     0x00380017U, \
-    0x44020001U,     0x00390023U,     0x44020001U,     0x003a0025U, \
-    0x44020001U,     0x003b0028U,     0x44020001U,     0x003c002aU, \
+    0x44020001U,     0x00390023U,     0x44020003U,     0x003c0025U, \
+    0x44020000U,     0x003c0028U,     0x44020000U,     0x003c002aU, \
     0x44020002U,     0x003e0003U,     0x44020000U,     0x003e0005U, \
     0x44020009U,     0x0047000cU,     0x44020006U,     0x004d000dU, \
     0x44020001U,     0x004e0015U,     0x44020001U,     0x004f0017U, \
-    0x44020002U,     0x00510023U,     0x44020001U,     0x00520025U, \
-    0x44020001U,     0x00530028U,     0x44020001U,     0x0054002aU, \
+    0x44020002U,     0x00510023U,     0x44020003U,     0x00540025U, \
+    0x44020000U,     0x00540028U,     0x44020000U,     0x0054002aU, \
     0x44020003U,     0x00570003U,     0x44020002U,     0x00590005U, \
     0x44020004U,     0x00020080U,     0x44030004U,     0x0006000cU, \
     0x44030000U,     0x0006000dU,     0x44030001U,     0x00070015U, \
     0x44030001U,     0x00080017U,     0x44030001U,     0x00090023U, \
-    0x44030001U,     0x000a0025U,     0x44030001U,     0x000b0028U, \
-    0x44030001U,     0x000c002aU,     0x44030002U,     0x000e0003U, \
+    0x44030003U,     0x000c0025U,     0x44030000U,     0x000c0028U, \
+    0x44030000U,     0x000c002aU,     0x44030002U,     0x000e0003U, \
     0x44030000U,     0x000e0005U,     0x44030009U,     0x0017000cU, \
     0x44030006U,     0x001d000dU,     0x44030001U,     0x001e0015U, \
     0x44030001U,     0x001f0017U,     0x44030002U,     0x00210023U, \
-    0x44030001U,     0x00220025U,     0x44030001U,     0x00230028U, \
-    0x44030001U,     0x0024002aU,     0x44030003U,     0x00270003U, \
+    0x44030003U,     0x00240025U,     0x44030000U,     0x00240028U, \
+    0x44030000U,     0x0024002aU,     0x44030003U,     0x00270003U, \
     0x44030002U,     0x00290005U,     0x44030005U,     0x00300080U, \
     0x44050000U,     0x00300003U,     0x44050002U,     0x00000003U, \
     0x44070000U,     0x00000003U,     0x44070002U,     0x00020003U, \
@@ -252,24 +252,24 @@
     0x44430001U,     0x00020080U,     0x444a0004U,     0x0006000cU, \
     0x444a0000U,     0x0006000dU,     0x444a0001U,     0x00070015U, \
     0x444a0001U,     0x00080017U,     0x444a0001U,     0x00090023U, \
-    0x444a0001U,     0x000a0025U,     0x444a0001U,     0x000b0028U, \
-    0x444a0001U,     0x000c002aU,     0x444a0002U,     0x000e0003U, \
+    0x444a0003U,     0x000c0025U,     0x444a0000U,     0x000c0028U, \
+    0x444a0000U,     0x000c002aU,     0x444a0002U,     0x000e0003U, \
     0x444a0000U,     0x000e0005U,     0x444a0009U,     0x0017000cU, \
     0x444a0006U,     0x001d000dU,     0x444a0001U,     0x001e0015U, \
     0x444a0001U,     0x001f0017U,     0x444a0002U,     0x00210023U, \
-    0x444a0001U,     0x00220025U,     0x444a0001U,     0x00230028U, \
-    0x444a0001U,     0x0024002aU,     0x444a0003U,     0x00270003U, \
+    0x444a0003U,     0x00240025U,     0x444a0000U,     0x00240028U, \
+    0x444a0000U,     0x0024002aU,     0x444a0003U,     0x00270003U, \
     0x444a0002U,     0x00290005U,     0x444a0004U,     0x00000080U, \
     0x444b0000U,     0x00000003U,     0x444b0002U,     0x00020003U, \
     0x444d0004U,     0x0006000cU,     0x444d0000U,     0x0006000dU, \
     0x444d0001U,     0x00070015U,     0x444d0001U,     0x00080017U, \
-    0x444d0001U,     0x00090023U,     0x444d0001U,     0x000a0025U, \
-    0x444d0001U,     0x000b0028U,     0x444d0001U,     0x000c002aU, \
+    0x444d0001U,     0x00090023U,     0x444d0003U,     0x000c0025U, \
+    0x444d0000U,     0x000c0028U,     0x444d0000U,     0x000c002aU, \
     0x444d0002U,     0x000e0003U,     0x444d0000U,     0x000e0005U, \
     0x444d0009U,     0x0017000cU,     0x444d0006U,     0x001d000dU, \
     0x444d0001U,     0x001e0015U,     0x444d0001U,     0x001f0017U, \
-    0x444d0002U,     0x00210023U,     0x444d0001U,     0x00220025U, \
-    0x444d0001U,     0x00230028U,     0x444d0001U,     0x0024002aU, \
+    0x444d0002U,     0x00210023U,     0x444d0003U,     0x00240025U, \
+    0x444d0000U,     0x00240028U,     0x444d0000U,     0x0024002aU, \
     0x444d0003U,     0x00270003U,     0x444d0002U,     0x00290005U, \
     0x444d0005U,     0x00000080U,     0x444f0000U,     0x00000003U, \
     0x444f0002U,     0x00160003U,     0x44ca0020U,     0x0036000cU, \

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

Xingyu Zhu said:
Given our customer don't have plan to upgrade SDK, need your help to provide a patch working on SDK0806.

Please take a look at the following patch for changes made from SDK 8.6 to SDK 9.1:

https://git.ti.com/cgit/processor-sdk/pdk/commit/packages/ti/drv/gpio/soc/j721s2/GPIO_soc.c?id=56f48eb92db3f993fadc1311ef0302610c601f45

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neerhar,
Thanks a lot! I'll try this patch and provide feedback later.

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

I will wait for your tests and feedback.

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neerhar,
This patch does not work on my case, Sciclient_rmIrqSet() return -1 as before.
Maybe there is some misconfigure in our sciclient boardcfg, i will dig into it.
Thansks a lot for your help! This ticket can be closed.

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Hi Zhao,

Feel free to follow up with any queries or questions.

Thanks,

Neehar

0 zhao li 2 months ago in reply to Neehar Sawant

Prodigy 180 points

Hi Neerhar,
T've figured it out and here is the logic chain:

intr router cfg muxcntl enable  failed due to id 145 in use
    ==> Sciclient_rmIrInpIsFree failed with id 145
         ==> Sciclient_rmIrqRouteValidate fail with ret -1
               => Sciclient_rmIrqFindRoute fail with ret -1
                   => Sciclient_rmProgramInterruptRoute fail with ret -1
                        => Sciclient_rmIrqSet fail with ret -1

Irq id 145 has been occupied by MAIN Domain:

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00600000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <145>, <146>, <147>, <148>, <149>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

This issue can be solved by removing irq id 145 from above MAIN Domain dts, though kernel outputs some warning logs.
Hoping this can help you and other guys.

Thanks
Zhao Li

0 Neehar Sawant 2 months ago in reply to zhao li

TI__Mastermind 19370 points

Thanks Zhao for the detailed response! I will look into this and create a patch or FAQ on this for future customers.

Thanks,

Neehar

Processors

Processors forum

TDA4AL-Q1: GPIO_socConfigIntrPath init fail in SDK0806