Tool/software:
Hi,
We are currently evaluating TLVM23625RDNR under the following conditions and would like to confirm the validity of our manual ripple voltage calculation as well as understand the discrepancy with the Webench simulation output.
【Conditions】
Vin = 24 V, Vout = 3.3 V, Iout = 2.5 A, Fsw = 800 kHz
Output capacitor: Effective capacitance 43 µF, ESR = 3 mΩ (from Webench)
Inductor: 2.2 µH internal
■ Q1: Could you please confirm whether the following calculation approach for output ripple voltage is appropriate based on the operating principles of TLVM23625RDNR?
① Inductor current ripple ΔIL
ΔIL = (VIN - VOUT) × (VOUT / VIN) / (L × Fsw)
= (24 - 3.3) × (3.3 / 24) / (2.2 µH × 800 kHz) ≒ 1.62 A
② Output ripple voltage ΔVout
ΔVout = ΔIL × (1 / (8 × Fsw × Cout) + ESR)
= 1.62A × (1 / (8 × 800 kHz × 43 µF) + 3 mΩ) ≒ 10.75 mV (p-p)
We would appreciate it if you could let us know whether this method and assumptions are valid for this device architecture.
■ Q2: Meanwhile, under the same conditions, Webench displays "Vout p-p = 6.44 mV", which is noticeably lower than the manually calculated result.
TLVM23625RDNR Webench
We suspect this discrepancy may be due to the following factors, but we would greatly appreciate clarification on what is actually taken into account in the Webench simulation:
-
Frequency-dependent ESR modeling or parasitic effects
-
Effective ESR optimization with parallel MLCC configuration
-
Ripple suppression through internal compensation loop
-
Averaging effects or waveform shaping in simulation models
Thank you very much for your support and guidance.
Conor
