PROCESSOR-SDK-J784S4: trigger GPIO interrupt by software

Hi Charles,

Are you testing with the same GPIO 11 pin? Or all GPIO pins?

Charles said:

I don't use the GPIO driver because it doesn't work for interruption to c7x (for this SDK) : J784S4XEVM: C7x GPIO Interrupt path issue - Processors forum - Processors - TI E2E support forums

Even with the CLEC offset changes you outlined, you were not able to generate an interrupt using the driver code?

Thanks,

Neehar

Hi Neehar,

Neehar Sawant said:

Are you testing with the same GPIO 11 pin? Or all GPIO pins?

I am using the same GPIO 11 pin. It works when i push the button but not when i write in the output data register.

Neehar Sawant said:

Even with the CLEC offset changes you outlined, you were not able to generate an interrupt using the driver code?

I didn't changed the driver code. I am using the CSL layer : 

Hi Charles,

I am currently out of office and will respond as soon as I am back, thank you for your patience!

Thanks, 

Neehar

Hi Neehar,

any update ?

Thanks,

Charles

Hi Charles,

Sorry for the delays as I am catching up on E2Es from being out of office, I will provide a response by the end of the week.

Thanks,

Neehar

Hi Charles,

Can you provide a dump of the GPIO registers?

Thanks,

Neehar

Hi Neehar,

This is the GPIO0 reg dump using CCS memory browser 

_PCR 0x600004 = 0x00000001

_BINTEN 0x600008 = 0x00000001

_DIR01 0x6000010 = 0xFFFFFFFF

_OUT_DATA01 0x6000014 = 0x00000800

_SET_DATA01 0x6000018 = 0x00000800

_CLR_DATA01 0x600001C = 0x00000800

_IN_DATA01 0x6000020 = 0xFFFFFFFF

_SET_RIS_TRIG01  0x6000024 = 0x00000800

_CLR_RIS_TRIG01  0x6000028 = 0x00000800

_SET_FAL_TRIG01 0x600002C = 0x00000000

_CLR_FAL_TRIG01 0x6000030 = 0x00000000

_INTSTAT01 0x6000034 = 0x00000000

_DIR01 0x6000010 = 0xFFFFF7FF

Thanks

Charles

Hi Charles,

Thanks for this dump. What is the return value from GPIO_socConfigIntrPath()?

Thanks,

Neehar

Hi Neehar,

I don't use the GPIO driver because it doesn't work due to the CLEC offset. Therefore I don't use GPIO_socConfigIntrPath().

I use the SCI and CSL API.

The interrupt path is config correctly. I can trigger the interrupt by pushing the SW3 button on the EVM (connected to the GPIO 11).

Thanks for your help.

Charles

Hi Charles,

Charles said:

The interrupt path is config correctly. I can trigger the interrupt by pushing the SW3 button on the EVM (connected to the GPIO 11)

I was asking as the INTSTAT register is not updated. Let me look into this further.

Thanks,

Neehar

Hi Neehar,

Do you have any update ?

Thanks

Charles

Hi Charles,

Sorry for the delay, have you set the interrupt to occur on the falling or rising edge trigger?

Thanks,

Neehar

Hi Neehar,

I set the rising edge bit and clear the falling edge bit.

Thanks

Charles

Hi Charles,

Neehar Sawant said:

I was asking as the INTSTAT register is not updated

Is the register dump after the interrupt has been triggered? Are you able to see any change in the INTSTAT01 register at all?

Thanks,

Neehar

Hi Neehar,

Neehar Sawant said:

Is the register dump after the interrupt has been triggered? Are you able to see any change in the INTSTAT01 register at all?

Yes, The register is dump after the interrupt has been triggered.

And I don't see any change at all.

Are you able to trigger the GPIO bank interrupt by software on your side ?

Thanks,

Charles

Hi Charles,

I have had not had any issues triggering GPIO interrupts by software. The example within the RTOS PDK does this as well with Main and WKUP GPIOs.

Are you testing with only one GPIO pin?

Can you confirm if the hwAttrs[].intCfg[].intNum is updated?

Thanks,

Neehar