TDA4VM: How to Configure UFS MCLK to 26 MHz on J721E (TDA4VM) – board-cfg Clock File Location & Procedure

peitao liu

Intellectual 590 points

Part Number: TDA4VM

Tool/software:

Hi TI Support Team,

we use sdk 10.

I’m working on a J721E (TDA4VM) and need to run the UFS controller’s MCLK at 26 MHz.

Using k3conf I see the relevant clock IDs:

root@j721e-evm:~# k3conf dump clock 277
|------------------------------------------------------------------------------|
| VERSION INFO |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024) |
| SoC | J721E SR1.1 |
| SYSFW | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|--------------------------------------------------------------------------------------------------------------------------------|
| 277 | 0 | DEV_UFS0_UFSHCI_HCLK_CLK | CLK_STATE_READY | 250000000 |
| 277 | 1 | DEV_UFS0_UFSHCI_MCLK_CLK | CLK_STATE_READY | 19200000 |
| 277 | 2 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 |
| 277 | 3 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 |
| 277 | 4 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 19200000 |
| 277 | 5 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 277 | 6 | DEV_UFS0_UFSHCI_MPHY_REFCLK | CLK_STATE_READY | 0 |
|--------------------------------------------------------------------------------------------------------------------------------|

Goal
• Make ID 1 (MCLK) use parent ID 3 (HFOSC1/EXT_REFCLK1) at 26 MHz.

5 months ago

0 Keerthy J 5 months ago

TI__Guru**** 164950 points

Hi,

I believe you are using a custom board. What is the oscillator clock frequency on your board?

- Keerthy

0 peitao liu 5 months ago in reply to Keerthy J

Intellectual 590 points

HI keerthy

We use 19.2MHz_8pF_10ppm

liupt

0 Keerthy J 5 months ago in reply to peitao liu

TI__Guru**** 164950 points

The above is the clock input and sources for UFS.

        ufs_wrapper: ufs-wrapper@4e80000 {
                compatible = "ti,j721e-ufs";
                reg = <0x0 0x4e80000 0x0 0x100>;
                power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 277 1>;
                assigned-clocks = <&k3_clks 277 1>;
                assigned-clock-parents = <&k3_clks 277 4>;
                ranges;
                #address-cells = <2>;
                #size-cells = <2>;

                ufs@4e84000 {
                        compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
                        reg = <0x0 0x4e84000 0x0 0x10000>;
                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                        freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
                        clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
                        clock-names = "core_clk", "phy_clk", "ref_clk";
                        dma-coherent;
                };
        };

peitao liu said:
| 277 | 3 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 |

Seems like this clock is not turned on as it shows 0. Are you this 26M (HFOSC1/EXT_REFCLK1) at 26 MHz?

- Keerthy

0 peitao liu 5 months ago in reply to Keerthy J

Intellectual 590 points

Hi Keerthy

What I want to ask is how to set DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT to 26M.

liupt

0 Keerthy J 5 months ago in reply to peitao liu

TI__Guru**** 164950 points

Hi,

I checked with our clock expert. Question is have you connected a 26M crystal oscillator to HFOSC1? If not from the HFOSC0 we will not be able to derive at 26M frequency accurately.

- Keerthy

+1 peitao liu 5 months ago in reply to Keerthy J

Intellectual 590 points

Hi Keerthy

Got it

Thank you

liupt

Processors

Processors forum

TDA4VM: How to Configure UFS MCLK to 26 MHz on J721E (TDA4VM) – board-cfg Clock File Location & Procedure