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AM2732-Q1: Can two QSPI devices be connected?

Part Number: AM2732-Q1
Other Parts Discussed in Thread: AM2732

Tool/software:

I'm working on an application where there is an MRAM or FeRAM device hooked to the processor.  These can be QSPI devices.  Is it possible to connect two devices to the QSPI interface, one NAND FLASH and one (or more) MRAM devices?

TIA,

-corey

  • Corey,

    There are a couple of concerns with connecting multiple QSPI devices to the same interface:

    The first is that there is only one QSPI-CS signal available on AM273.  You will need to add control logic to ensure the intended QSPI device gets the CS signal.

    The second is that you need to do some sort of muxing on the lines so that only one signal path to one QSPI devices is physically connected at a time. You cannot simply route to both QSPI devices and the AM273 like you would for a multi-device I2C interface.  Invariably, one of of the QSPI devices will be wired up in such a way that you get stubs on the signal path (where the connections to the other QSPI device are made).  These stubs will cause reflections on the signal path and destroy your signal integrity.  You can add a high speed mux (make sure it has sufficient bandwidth for the QSPI frequencies you plan to use) and use this as a switch to connect between the two QSPI devices.  This can be routed in the PCB in such a way that no stubs exits on the signal paths to either of the QSPI devices.

    The third concern (if you implement the above) is that if you are intending to use QSPI boot, you need to ensure the default signal path on the mux connects to the QSPI device you intend to boot from.  This needs to be done using pullups or similar on the control lines as this would need to be configured before the AM273 device boots up and can start controlling any signal paths.

    Thanks,
    Mike

  • Thanks Mike,

    Muxing the CS line would be pretty easy, I think.  Just a mux or some gates tied to a GPIO that defaults to the FLASH device.

    Muxing the other lines sounds more challenging.  The lines are bidirectional and knowing which direction each line is would be hard.  In addition, getting the timing working on that would be a challenge.  You would need something that understood the protocol, not just a bidirectional mux tied to a GPIO.

    I could run the lines where they go in one side of a pad and out the other.  You then have a big impedance change at that point, but not a stub.  I guess I could make the traces the size of a pad to eliminate that.  You would still have the pin on the chip that would be sort of stub-ish.  I believe the IO lines in QSPI go high impedance when not in use.

    Anyway, that helps a bunch; that give me something to work with.

    -corey

  • I could run the lines where they go in one side of a pad and out the other.

    This wouldn't work.  If you think about the PCB layout being simplified to the below, where the traces run into one side of the Flash A pads and out the other to Flash B:

    AM273-----Flash A-----Flash B

    Communicating to Flash B would be fine.  However, communicating to Flash A would have the trace length from A to B acting as a stub adding the reflections.

    You would need to use a mux like this part:  TS3DDR3812RUAR

    It has the bandwidth and the timing on all the signals through the mux would be the same, so as long as you route all the signals through the mux, there should not be any worries there.

    Thanks,
    Mike

  • Ah, yes, you would need some sort of termination at the end of the line.  Of course.

    > You would need to use a mux like this part:  TS3DDR3812RUAR

    Ok, thanks for the reference.  I'm not sure how it knows which direction the data is going, but you have the same issue with DRAM.

    Thanks again, Mike.

    -corey

  • Oh, that's a switch, not a gate type mux.  Ok, makes perfect sense.

  • I thought some more about this, and I've had some crazy ideas.

    These chips all have the same layout.  If you put one on the bottom of the board and flip it around, the corresponding pins would be very close to each other.  The middle 4 pins, including the clock, are about 1.5mm apart, and then 1.5mm to go through the board, so 3mm total.  The IO0 pin would have about 5.5mm total to go since it's on the end of the chip.  If you assume propagation is .5C (probably closer to .66C), 3mm is about 20ps, and 5.5mm is about 36ps.  At 133MHz the clock is ~7.5ns.  So that's probably not a problem for the I/O lines.

    For the clock, I'm not sure, I assume the risk there is double clocking.  As I understand it, the series resistor will allow half VIO in at the beginning, the signal will propagate, then reflect, where the voltage will double, then hit the series resistor again.  The clock signal in the middle will see 1/2 VIO, then 40ps later it will go to VIO.

    Except in reality these lines have capacitance and it's going to take some time to charge them.  The rise times on these signals is probably going to be around 300ps from what I can find in the data sheet.  So again, I'm not sure how much this matters.

    As it is the longest line from the series resistor to the IO pin is about 5mm.

    My other crazy idea was to do a Y connection and put a series resistor on each leg of the Y and another series resistor half the value of the others on the main leg.

    Another thing I wondered now is where to put the series resistor.  In my current layout those resistors are directly between the AM2732 and the QSPI device, both as close as they can be, so in reality they are in the middle of the full signal path.  And there's nothing I can do about that except move the QSPI device farther from the chip, which seem silly.  These distances are so short I'm not sure what matters.

    Anyway, crazy ramblings from a possibly crazy person

    Thanks again.