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C6A8168 SERDES_CLK input - LVDS or HCSL?

Robert F.
Intellectual 855 points
Other Parts Discussed in Thread: CDCM61002

Hello,

The clock generator used in evm816x_Schematics_RevE.pdf (CDCM61002) has LVDS outputs. Can I use HCSL output clock generator and connect it directly to SERDES_CLK pins of C6A8168?

Thank you,

- Robert

 

  • 0
    Intellectual 855 points

    I found this in datasheet (document SPRS680A):

    When the PCIe interface is used, the SERDES_CLKN/P clock is required to meet the REFCLK AC
    specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and Gen.2). When
    the SATA interface is used, the SERDES_CLKN/P clock is required to meet the specifications in
    Table 7-7. When both the PCIe and SATA interfaces are used, both sets of specifications must be met
    simultaneously.

    An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI
    Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In
    addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown
    in Table 7-8, are also acceptable.

    I believe this means, yes, I can connect an HCSL  clock generator to the SERDES_CLKN/P pins via 100nF series capacitors. Am I right?

  • 0 in reply to Robert F.
    TI__Mastermind 25055 points

    Robert,

    A high-quality, low-jitter 100-MHz differential clock source is required for the PCIe and SATA PHYs, so as you described above, the key is that it must meet the specifications as described in the SERDES_CLKN/P Input Clock section of the datasheet.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Intellectual 855 points

    Thank you Marc. I used CY24292 configured as HCSL (PCIE).