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SK-AM62B-P1: Clarification Needed on SoC UART1 FET Switch & Buffer Section in SK-AM62B-P1 Schematic

Part Number: SK-AM62B-P1

Tool/software:

Hellow Ti experts,

I’m currently designing a custom single-board computer (SBC) based on the SK-AM62B-P1 EVM as a reference. While working on the schematic, I’ve encountered some confusion regarding the SoC UART1 FET switch & buffer section (as shown on page 37 of the EVM schematic).
8176.PROC142A(002)_SCH_With_Design_Updates..Notes_V1.0.pdf

I’ve noticed that signals from SoC_UART1 are routed to multiple blocks:

  • The FT4232 USB-to-UART bridge section

  • The user expansion connector

  • And are also routed through a FET switch/multiplexer, alongside SoC_SPI2 signals.

I’m trying to fully understand the connection topology and purpose of this section:

  • How is the switching logic controlled?

  • What determines whether UART1 connects to the FT4232 vs. the expansion connector?

  • Why are SPI2 and UART1 sharing this switching structure?

A detailed explanation or block-level overview of how this section operates would be greatly appreciated.

Thank you
Arijit