Original question:
[FAQ] AM64X/ AM62X : How to Reset the SOC when WDT timer expires in AM64X and AM62X?
Tool/software:
The existing examples on MCU R5 SDL RTI UC1 when watchdog expires, it will go to abort and exit but it wont reset the whole thing.
How to modify the examples so that when watchdog happen it reset the whole thing
Hello Jm Moon,
We need to configure the MMR register and route an WDT event to the ESM module to reset the SOC.
Please follow the steps below and see if this works or not in your application.
CTRL MMR configuration :
Call the API below to confirm the MMR region setting.
/* Reset Ctrl belongs to partition 6 of the CTRL MMR */
uint32_t rstPartition = 6U;
uint32_t volatile * ctrl_addr ;
/* Unlock CONTROL MMR registers */
SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_WKUP, rstPartition);
ctrl_addr = (volatile uint32_t *)(0x43018170);
*ctrl_addr &= (~(1<<17));
/* Lock CONTROL MMR registers */
SOC_controlModuleLockMMR(SOC_DOMAIN_ID_WKUP, rstPartition);
ESM Configuration :
This is already set in the UC1 example.
So, try to configure the above CTRM MMR setting and see if this works or not.
Regards,
Anil.
Hi Anil,
My current setup is using MCU R5 core
I tested with below changes to set MMR register for MCU core, am I doing the right thing? I can see the board reset after WDOG timeout
