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PROCESSOR-SDK-AM64X: AM64x PCIe in EC and EP mode

Mahantesh Mahantesh
Prodigy 70 points
Part Number: PROCESSOR-SDK-AM64X

Tool/software:

Hi Team

I have configured TI AM64x board  as RC and another TI AM64x board configured as EP. These two boards are connected each other through PCIe interface.  TI AM64x RC  mode < ----- > TI AM64x EP mode.

I want RC to send interrupt to EP. I gone through the below stuff from TI AM64x reference manual below explanation

Explanation is as below. I want to know where is this VENDOR_SPECIFIC_CONTROL_REG is located . I want to write value to the register.

12.2.2.4.4.3.1 PCIe Core Downstream Interrupts The Vendor Specific Capability signal of the PCIe core, F0_VSEC_INTERRUPT_OUT, is used to generate interrupts to the EP from the RP. The F0_VSEC_INTERRUPT_OUT represents the interrupt for the EP Physical Function 0. This signal is used to generate the PCIE_DOWNSTREAM_PULSE interrupt to the local host. The RP can write to the Vendor Specific Control registers (PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG) to assert this signal at the EP and this will trigger the PCIE_DOWNSTREAM_PULSE interrupt to the EP host. 

Please can some tell me where VENDOR_SPECIFIC_CONTROL_REG is located ?

Regards

Mahantesh

  • 0 in reply to James Pair
    Prodigy 70 points

    I got below changes for AM64x. Still i did not get the downstream_pulse interrupt from RC to EP

    @@ -566,11 +566,13 @@ &mailbox0_cluster7 {
    };

    &pcie0_rc {
    + //status = "okay";
    status = "disabled";
    };

    &pcie0_ep {
    - status = "disabled";
    + //status = "disabled";
    + status = "okay";
    };

    diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
    index 40256815e8..7cd246859f 100644
    --- a/drivers/pci/controller/cadence/pci-j721e.c
    +++ b/drivers/pci/controller/cadence/pci-j721e.c
    @@ -134,6 +134,12 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
    return IRQ_HANDLED;
    }

    +static irqreturn_t j721e_pcie_downstream_irq_handler(int irq, void *priv)
    +{
    + printk("debug: MAHA downstream irq handled");
    + return IRQ_HANDLED;
    +}
    +
    static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
    {
    u32 reg;
    @@ -507,7 +513,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
    u32 mode;
    int ret;
    int irq;
    -
    + int down_irq;
    + printk("DBG1000 MAHA inside j721e_pcie_probe2 \n");
    data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
    if (!data)
    return -EINVAL;
    @@ -545,6 +552,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
    if (irq < 0)
    return irq;

    + down_irq = platform_get_irq_byname(pdev, "downstream_pulse");
    + if (down_irq < 0)
    + return down_irq;
    dev_set_drvdata(dev, pcie);
    pm_runtime_enable(dev);
    ret = pm_runtime_get_sync(dev);
    @@ -566,6 +576,15 @@ static int j721e_pcie_probe(struct platform_device *pdev)
    goto err_get_sync;
    }

    + ret = devm_request_irq(dev, down_irq, j721e_pcie_downstream_irq_handler, 0,
    + "j721e-pcie-downstream-irq", pcie);
    + if (ret < 0) {
    + dev_err(dev, "failed to request downstream pulse IRQ %d\n", ret);
    + return ret;
    + }
    +
    + printk(" ********* DBG500 down_irq == %d\n", down_irq);
    +
    j721e_pcie_config_link_irq(pcie);

    switch (mode) {