Tool/software:
Hi Team I did below changes for AM64x to send MSI interrupt from RC to RP. But still i did not get downstream_interrupt. I mean handler for this interrupt did not execute on EP SoC
Please can you suggest what is next debugging is required . I Used setpci -s 0001:01:00.0 ECAP_VNDR+8.l=100 to fire the interrupt. Still i am not gettinng the interrupt
@@ -566,11 +566,13 @@ &mailbox0_cluster7 {
};
&pcie0_rc {
+ //status = "okay";
status = "disabled";
};
&pcie0_ep {
- status = "disabled";
+ //status = "disabled";
+ status = "okay";
};
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 40256815e8..7cd246859f 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -134,6 +134,12 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
return IRQ_HANDLED;
}
+static irqreturn_t j721e_pcie_downstream_irq_handler(int irq, void *priv)
+{
+ printk("debug: MAHA downstream irq handled");
+ return IRQ_HANDLED;
+}
+
static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
{
u32 reg;
@@ -507,7 +513,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
u32 mode;
int ret;
int irq;
-
+ int down_irq;
+ printk("DBG1000 MAHA inside j721e_pcie_probe2 \n");
data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
if (!data)
return -EINVAL;
@@ -545,6 +552,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
+ down_irq = platform_get_irq_byname(pdev, "downstream_pulse");
+ if (down_irq < 0)
+ return down_irq;
dev_set_drvdata(dev, pcie);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
@@ -566,6 +576,15 @@ static int j721e_pcie_probe(struct platform_device *pdev)
goto err_get_sync;
}
+ ret = devm_request_irq(dev, down_irq, j721e_pcie_downstream_irq_handler, 0,
+ "j721e-pcie-downstream-irq", pcie);
+ if (ret < 0) {
+ dev_err(dev, "failed to request downstream pulse IRQ %d\n", ret);
+ return ret;
+ }
+
+ printk(" ********* DBG500 down_irq == %d\n", down_irq);
+
j721e_pcie_config_link_irq(pcie);
switch (mode) {
