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AM623: Layout differences between LPDDR4/DDR4 RE: CRC

Blake Carpenter
Expert 7005 points
Part Number: AM623
Other Parts Discussed in Thread: AM62L, SYSCONFIG

Tool/software:

Hi Support, 

Can you take a look at the following Assigned Focus Customer Question:

In the DDR layout guidelines, we have the following:

Can you please confirm that this would not apply to us since we are using LPDDR4 and not DDR4? 

If we were using DDR4, does the controller/PHY in the AM62Lx even support CRC? 

I believe this document is generic and therefore covers scenarios/features for many other devices, which may not be applicable to our case; can you confirm?

Thanks!

Blake

  • 0
    TI__Expert 5525 points

    Greetings Blake,

    Just to make sure we're talking about the right device, are you using AM62x or AM62Lx? They share board design and layout guidelines but are two distinct devices.

    Sincerely,

    Lucas

  • 0 in reply to Lucas Bowe
    TI__Expert 7005 points

    Hi Lucas, AM62L - Good catch!  apologies.

    Blake

  • 0 in reply to Blake Carpenter
    TI__Expert 5525 points

    Greetings Blake,

    Thanks for the clarification. There is an updated version of these guidelines from that screenshot I think, though it pretty much says the same things:

    As far as the byte swap and bit swizzling limitations, this should be accurate for LPDDR4. The sysconfig tool is the best way to configure this error-free, screenshot shown below:

    It will make sure the bit swapping/swizzling logic is not violated (the drop down items adjust).

    Regarding CRC, the IP should work with JEDEC compliant DDR4 memories that support CRC errors over the ALERT_n pin, though it is a little fuzzy on if the controller needs to have it explicitly enabled as a feature.

    Sincerely,

    Lucas

  • 0 in reply to Lucas Bowe
    TI__Expert 7005 points

    Hi Lucas, 

    Oops!  Looks like a typo derailed us:

    It seems like my question was not clear and that’s because of my typos in my original email. 

    The snippet I posted in my first email was from the DDR design guide, under the DDR4 section. 

    We are not using DDR4. We are using LPDDR4. 

    In the LPDDR4 section, there is no mention of the not being able to use CRC if bit swapping is done. 

    So, my question is: Is CRC supported when using LPDDR4? 

    If yes, then would the same note apply, where we cannot use CRC if we do bit swapping with LPDDR4? 

    From what I can tell from the datasheet and reference manual, there is no CRC for LPDDR4, but there is in-line ECC.


    Apologies - should have sanity checked it better.

    Have a great weekend!

    Blake

  • 0 in reply to Blake Carpenter
    TI__Expert 5525 points

    Greetings Blake,

    No worries! CRC is not apart of the JEDEC LPDDR4 specification, so there's no standard hardware support for it in LPDDR4 or the controller. If you want to do CRC checking on the data stored in DRAM, it'd be in an higher level software abstraction layer. From the perspective of an ARM core, bit swizzling/byte swapping is invisible (it's all handled in the DDR IP itself).

    You are correct about in-line ECC being present, this is hardware managed ECC that basically stores the ECC codes inside the DRAM (so living side by side with data) and it uses these codes for single error correction+ double error detection (SECDED). This reduces the amount of DRAM available but allows for error checking to be done by hardware.

    Have a great weekend as well!

    Sincerely,

    Lucas