Hi YL,

I really doubt this is related to display timing issue, i think we have seen similar issue even with the default SDK. Let me check the fix in the latest release and share it with you.

Regards,

Brijesh

Hi YL,

Can you please disable mhdp from vision apps dtb file, rebuild dtb file and try it out?

+&mhdp {
+ status = "disabled";
+};
+

Regards,

Brijesh

Hi, Brijesh,

I install the linux sdk of ti-processor-sdk-linux-adas-j721s2-evm-10_01_00_04-Linux-x86-Install.bin.

Do you mean add above config to k3-j721s2-vision-apps.dtso on path of board-support\ti-linux-kernel-6.6.44+git-ti\arch\arm64\boot\dts\ti?

// SPDX-License-Identifier: GPL-2.0
/*
 * vision-apps: device-tree overlay
 *
 * Copyright (C) 2019 - 2021 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include "k3-j721s2-rtos-memory-map.dtsi"
#include <dt-bindings/gpio/gpio.h>

&main_i2c1 {
    status = "disabled";
};

&main_i2c4 {
	status = "disabled";
};

&main_i2c5 {
	status = "disabled";
};

&serdes_wiz0 {
    status = "disabled";
};

&dss {
    status = "disabled";
};

&ti_csi2rx0 {
    status = "disabled";
};

&ti_csi2rx1 {
    status = "disabled";
};

&exp_som {
	P5_hog {
		gpio-hog;
		gpios = <5 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "GPIO_eDP_ENABLE";
	};
};
// add below config
&mhdp {
 status = "disabled";
};

Thanks,

YL

Hi YL,

Yes, can you add the changes that i shared earlier to this dtb file, generate vision apps dtbo file and then copy it in the BOOT folder.

Regards,

Brijesh

Hi, Brijesh,

After add this patch, the SCICLIENT seems fix.

But meet another issue, that post below.

[MCU2_0] 23.892088 s: DSS: ERROR: Dctrl default init failed !!!

Could you help us to check what reason making this?

Thanks,

YL

[MCU2_0]     23.271866 s: DSS: Init ... !!!
[MCU2_0]     23.271884 s: DSS: Display type is eDP !!!
[MCU2_0]     23.271908 s: DSS: M2M Path is enabled !!!
[MCU2_0]     23.271926 s: DSS: SoC init ... !!!
[MCU2_0]     23.271942 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
[MCU2_0]     23.272019 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272042 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
[MCU2_0]     23.272175 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272195 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
[MCU2_0]     23.272357 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272378 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
[MCU2_0]     23.272482 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272502 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
[MCU2_0]     23.272591 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272612 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
[MCU2_0]     23.272687 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.272709 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=594000000
[MCU2_0]     23.272839 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     23.272865 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2
[MCU2_0]     23.272960 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     23.272983 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2
[MCU2_0]     23.273109 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     23.273131 s: DSS: SoC init ... Done !!!
[MCU2_0]     23.273149 s: DSS: Board init ... !!!
[MCU2_0]     23.273165 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!!
[MCU2_0]     23.818891 s: DSS: Turning on DP_PWR pin for eDP adapters ... Done!!!
[MCU2_0]     23.818924 s: DSS: Board init ... Done !!!
[MCU2_0]     23.891960 s: src/drv/dctrl/dss_dctrlExtended.c @ Line 630:
[MCU2_0]     23.891993 s: error : DP_SetVic
[MCU2_0]     23.892016 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1177:
[MCU2_0]     23.892038 s: Set VP parameters IOCTL failed
[MCU2_0]     23.892088 s: DSS: ERROR: Dctrl default init failed !!!
[MCU2_0]     23.892112 s: DSS: Init ... Done !!!

Hi, Brijesh,

We add some debug log to trace root cause.

The error result come from the function of calculateTuParams on dp_if.c and the code path of pdk_j721s2_10_01_00_25\packages\ti\drv\dss\src\csl\dp\src.

Do you have any idea for fix this issue?

Thanks,

YL

    /* Link bandwidth is oversubscribed. */
    if (currValidSym >= 64U) {
        retVal = CDN_ENOTSUP;
        printf("[%s, %d] retVal: %d\r\n", __func__, __LINE__, retVal);
    }

Hi YL,

That's strange.. "/* Link bandwidth is oversubscribed. */", we dont oversubscribe link bandwidth... Not exactly sure why this is coming. 

Are you checking this on EVM? If not, what is connected at the eDP output? Is there a serializer? 

Regards,

Brijesh 

Hi, Brijesh,

Yes, we use the TDA4AL EVM for testing. And eDP output connect to display monitor.

Also, I print the laneCount and symbolRate on calculateTuParams.

Does it setting are correct?

[calculateTuParams, 433] laneCount: 2, symbolRate: 162.000000

Update:

Checked the function of Dss_dctrlDrvInitDPTX on dss_dctrlExtended.c

The default definition as below:

static int32_t Dss_dctrlDrvInitDPTX(uint32_t isHpdSupported, uint32_t multilinkPhyType)
{
    Dss_DctrlDisplayPortDrvObj *pObj;
    uint32_t memReqDp, memReqDpPhy;
    HwiP_Params hwiParams;
    uint32_t dpApiRet;
    int32_t retVal = FVID2_SOK;

    pObj = &gDssDctrlDisplayPortDrvObj;

    pObj->dpCfg.regBase      = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;
    pObj->dpCfg.regBaseSapb  = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE;
#if defined (SOC_J784S4) || defined (SOC_J742S2)
    pObj->dpPhyCfg.regBase   = (uint32_t*)CSL_WIZ16B8M4CT3_4_WIZ16B8M4CT3_BASE;
#else
    pObj->dpPhyCfg.regBase   = (uint32_t*)CSL_SERDES_10G0_BASE;
#endif
    pObj->dpPhyCfg.regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;

    pObj->dpFWImage.iMem     = gDctrlDpIram;
    pObj->dpFWImage.iMemSize = DCTRL_DP_IMEM_SIZE;
    pObj->dpFWImage.dMem     = gDctrlDpDram;
    pObj->dpFWImage.dMemSize = DCTRL_DP_DMEM_SIZE;

    pObj->dpCbInfo.event     = NULL;
    pObj->dpClkInfo.mhz      = 125;
#if defined (SOC_J721S2)
    pObj->srcCaps.maxLinkRate = DP_LINK_RATE_2_70;
    pObj->srcCaps.laneCount   = 2;
#else
    pObj->srcCaps.maxLinkRate = DP_LINK_RATE_8_10;
    pObj->srcCaps.laneCount   = 4;
#endif
    pObj->srcCaps.ssc               = BFALSE;
    pObj->srcCaps.scramblerDisable  = BFALSE;
    pObj->srcCaps.tps3              = BTRUE;
    pObj->srcCaps.tps4              = BTRUE;
    pObj->srcCaps.fastLinkTraining  = BFALSE;
    pObj->srcCaps.maxVoltageSwing   = 3;
    pObj->srcCaps.maxPreemphasis    = 2;
    pObj->srcCaps.forceVoltageSwing = BFALSE;
    pObj->srcCaps.forcePreemphasis  = BFALSE;
    pObj->srcCaps.laneMapping       = DP_LANE_MAPPING_SINGLE_REGULAR;
    pObj->srcCaps.controllersPerPhy = DP_SINGLE_CONTROLLER;

    pObj->isConnected               = UFALSE;
    pObj->videoState                = DP_VIDEO_STATE_IDLE;

    pObj->isHpdSupported            = isHpdSupported;

    pObj->hpdPending                = UFALSE;
    pObj->hpdInProgress             = UFALSE;

Thanks,

YL

Hi YL,

yl chen said:

[calculateTuParams, 433] laneCount: 2, symbolRate: 162.000000

Not sure about sumbolrate, but lane count is matchin, we use 2 lanes on J721S2. 

Does this issue come consistently? Could you share the complete log? 

Regards,

Brijesh

Hi, Brijesh,

Could you have provide the suggest the timings settings?

We needs the width size is 3840 and height size is 2160.

Thanks,

YL

        prm.timings.width        = 3840U;
        prm.timings.height       = 2160U;
        prm.timings.hFrontPorch  = 176U;
        prm.timings.hBackPorch   = 296U;
        prm.timings.hSyncLen     = 88U;
        prm.timings.vFrontPorch  = 8U;
        prm.timings.vBackPorch   = 72U;
        prm.timings.vSyncLen     = 10U;
        prm.timings.pixelClock   = 594000000ULL;

Hi, Brijesh,

Upload log for you check.

7673.putty.log

Hi YL,

From RTOS side, we have not really validated 4K resolution, but might be validated on Linux, checking with the Linux team. 

Regards,

Brijesh

Hi, Brijesh,

OK, thanks, Waiting your good news.

Thanks,

YL

Hi, Brijesh,

I find the information of DSS as below link.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j721s2/10_01_00_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html

In 3.2.2.6. DSS

I am confused this information, does it support 4K@60FPS in linux side?

But I seems that have the hardware limitation on J721S2 platform only support to 4K@30FPS.

Thanks,

YL

Hi YL,

Confirmed with the team that Linux does support 4K resolution at 30fps, as given in above screen shot. 

Regards,

Brijesh

Hi, Brijesh,

It is good news.

So, could you help to provide the profile display timing setting successfully to bring up in linux side for reference like as below?

prm.timings.width = 3840U;
prm.timings.height = 2160U;
prm.timings.hFrontPorch = 88U;
prm.timings.hBackPorch = 148U;
prm.timings.hSyncLen = 44U;
prm.timings.vFrontPorch = 4U;
prm.timings.vBackPorch = 36U;
prm.timings.vSyncLen = 5U;
prm.timings.pixelClock = 297000000ULL;

Thanks,

YL

Hi YL,

but this timing is dependent on your display device, so can you please get it from your display device and then use it from the RTOS driver? 

Regards,

Brijesh

Hi, Brijesh,

I have not the 4K monitor to test it.

I think this issue of calculateTuParams be affect by monitor spec.

What you think?

Thanks,

YL

hi YL,

But how are you then testing out 4K resolution? Which resolution is your monitor supporting? Can you try the resolution that monitor supports? 

Regards,

Brijesh

Hi, Brijesh,

My monitor only support the 1920x1200 resolution. I will try to set this size to check the display function.

Thanks,

YL

Sure YL.