AM69A: SDK11 - EnableCustomLayer issue

Azer Tiop

Part Number: AM69A

Tool/software:

Hello,

SDK : PROCESSOR-SDK-RTOS-J784S4 11.00.00.06 (May 22, 2025)

First of all, I wanted to thank you for taking my feedback on the problems related to the custom layer in SDK10 into consideration. I see the modifications in version 11.

Now, I am facing an issue that I didn't have in the previous version.

To enable the custom layer, I just needed to change enableCustomLayers variable to 1 (see photo).

However, when I print the output value at this point (photo), I see 0 as the output.

Could it be that you made another modification to the SDK that prevents changes to this variable from being considered?

To build the project, I start in utils.tidlModelImport with make command.

Then in c7x-mma-tidl, I build with TARGET_PLATFORM=PC make tidl

Note: I noticed that the compilation only works if we build for PC emulation. With a build for the target, an error appears 'Could not load library libvx_tidl_rt.so'.

Regards,

AZER

3 months ago

0 Christina Kuruvilla 3 months ago

TI__Expert 4610 points

Hi Azer,

Let me do some investigating with Dev team and see if this is a bug or if they have a workaround for this issue.

Warm regards,

Christina

0 Christina Kuruvilla 3 months ago in reply to Christina Kuruvilla

TI__Expert 4610 points

Hi Azer,

In the new 11.0 release, the custom layer support has been extended to OSRT flow, instead of being only on TIDLRT flow as before. Due to this, in advanced osrt_options there is a parameter called enable_custom_layer , which is set to 0 as a default. If the user changes the default value to 1, the 11.0 default values will still be overwritten by the enable_custom_layer parameter from the osrt_options to keep showing 0.

The workaround to enable the custom layer process flow is to set the enable_custom_layer parameter to be set to 1, which can be found under the edgeai-tidl-tools common_utils.py file (under examples)

Could you also share the target build error compilation output logs to better understand what the issue is?

Warm regards,

Christina

0 Azer Tiop 3 months ago in reply to Christina Kuruvilla

Intellectual 350 points

Hi Christina,

Thank you for your response. My custom layer is now recognized, but I am still encountering an error. Could you please take a look at it?

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              11_00_06_00             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              11_00_00_00             |
-------------------------------------------------------------------------------

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options

CurrLayerName = sequential_17/max_pooling2d_22/MaxPool

-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       8 |                       1 |
| CPU                     |                       0 |                       x |
-------------------------------------------------------------------------------
============================= [Parsing Completed] =============================

In TIDL_tfliteRtImportInit subgraph_id=19
 
==================== [Optimization for subgraph_19 started] ====================

In TIDL_runtimesOptimizeNet: LayerIndex = 10, dataIndex = 9 
----------------------------- Optimization Summary -----------------------------
-------------------------------------------------------------------------------------
|            Layer           | Nodes before optimization | Nodes after optimization |
-------------------------------------------------------------------------------------
              
| TIDL_CustomLayer           |                         3 |                        3 |
| TIDL_PoolingLayer          |                         2 |                        2 |
-------------------------------------------------------------------------------------

Total nodes in subgraph: 10

=================== [Optimization for subgraph_19 completed] ===================

In TIDL_runtimesPostProcessNet 
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
 0.7s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
 0.11s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
 0.137s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP_C7-2
 0.1508s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 
 0.1538s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 
 0.1582s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 
 0.1609s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 
 0.1654s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 
 0.1694s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 
 0.1721s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 
 0.1762s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 
 0.1799s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 
 0.1834s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 
 0.1859s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 
 0.1890s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 
 0.1918s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2 
 0.1941s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_2 
 0.1968s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_3 
 0.1991s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_4 
 0.2014s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_5 
 0.2040s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_6 
 0.2063s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_7 
 0.2089s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_8 
 0.2115s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3 
 0.2137s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_2 
 0.2179s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_3 
 0.2207s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_4 
 0.2240s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_5 
 0.2265s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_6 
 0.2290s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_7 
 0.2317s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-3_PRI_8 
 0.2347s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4 
 0.2375s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_2 
 0.2401s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_3 
 0.2426s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_4 
 0.2454s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_5 
 0.2482s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_6 
 0.2509s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_7 
 0.2534s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-4_PRI_8 
 0.2564s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 
 0.2591s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 
 0.2617s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 
 0.2644s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 
 0.2674s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 
 0.2701s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 
 0.2739s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 
 0.2776s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 
 0.2823s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 
 0.2858s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 
 0.2894s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 
 0.2933s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 
 0.2969s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 
 0.3008s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 
 0.3045s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE9 
 0.3080s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE10 
 0.3119s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE11 
 0.3298s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE12 
 0.3344s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 
 0.3383s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 
 0.3427s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 
 0.3474s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 
 0.3511s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 
 0.3552s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 
 0.3589s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 
 0.3628s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 
 0.3675s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC1_FC 
 0.3718s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 
 0.3762s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 
 0.3800s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 
 0.3846s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 
 0.3894s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 
 0.3935s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU4-0 
 0.3980s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_NF 
 0.4018s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_LDC1 
 0.4058s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_MSC1 
 0.4101s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_MSC2 
 0.4139s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_VISS1 
 0.4196s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC2_FC 
 0.4240s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU4-1 
 0.4245s:  VX_ZONE_INFO: [tivxInit:152] Initialization Done !!!
 0.4250s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
************ TIDL_subgraphRtCreate done ************ 
[interpreter.py][allocate_tensors]
  0%|                                                     | 0/4 [00:00<?, ?it/s](11, 61)

 tidl_tfLiteRtImport_delegate.cpp Invoke 544 
*******   In TIDL_subgraphRtInvoke  ******** 
 0.49893s:  VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0
 0.49902s:  VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0
 0.49905s:  VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0
 0.49910s:  VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff
 0.49916s:  VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0
 0.49923s:  VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0
 0.49930s:  VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0

Regards,

Azer

0 Christina Kuruvilla 3 months ago in reply to Azer Tiop

TI__Expert 4610 points

Hi Azer,

Could I see your import config and model? I would like to check over your settings. If you don't want to post on E2e, you can send it through email (c-kuruvilla@ti.com)

Also, are you seeing the issue you mentioned in your post where the compiling only works on PC emulation and not device still?

Warm regards,

Christina

0 Azer Tiop 2 months ago in reply to Christina Kuruvilla

Intellectual 350 points

Hi,

I sent you all the information by email. Did you receive it?

Thanks and regards,

Azer

0 Christina Kuruvilla 2 months ago in reply to Azer Tiop

TI__Expert 4610 points

Hi Azer, I did not. Could you possible resend?

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AM69A: SDK11 - EnableCustomLayer issue