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C5535 DSP

microt
Intellectual 310 points

My ISR on INT0 and INT1 triggers on falling edge.

Is there any register to change this to rising edge

  • 0
    Intellectual 310 points

    Hi

    Would somebody from TI please reply to this post

    Thanks

  • 0
    TI__Mastermind 30110 points

    Hi Microt,

    Sorry for the delay.

    The interrupt signals on the external interrupts pins (INT0 and INT1) are detected with a synchronous negative edge detector circuit. To reliably detect the external interrupts, the interrupt signal must have at least 2 SYSCLK high followed by at least 2 SYSCLK low.

    INT0 and INT1 require external pull-ups.

    So I do not think you can interrupt on a rising edge.

    GPIO interrupts are falling or rising edge triggered interrupts.

    I will confirm with the design team.

    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Mastermind 30110 points

    Hi Microt,

    I have confirmed that INT0/1 must be on falling edge as documentation dictates. Sorry.

    Some glue logic (mosfet) can invert the polarity of your INT source. Or GPIO interrupt if it works for you.

    Best Regards,
    Mark