Tool/software:
The EMIF16 is configured in SS mode, with two chip enable signals, CE0 and CE1, enabled simultaneously. A 16-bit write cycle on CE0 takes approximately 208 ns.
The figure above shows the delay issue:
Configuration:
- Waveform 0: CE0
- Waveform 1: CE1
- Waveform 2: WE
- Waveform 3: OE
- Waveform 4: External input IO signal
- Waveform 5: External input interrupt function
In the main function, data is continuously written to CE0, with each write being a 16-bit cycle. When the external input IO signal triggers a high level, the system enters the interrupt service routine (ISR). The ISR (priority level 0x16) first writes two 16-bit data items to CE1, and then reads one 16-bit data from CE1.
Issue Description:
- The trigger of the interrupt service routine was delayed by approximately 12 EMIF16 CE0 write cycles, during which time the CE0 data transfer was being processed.
- When writing to CE1, i.e., when switching the chip enable from CE0 to CE1, another delay occurred, approximately 26 EMIF16 CE0 write cycles, during which time the CE0 data transfer was still being processed.
Inside the main loop, data is continuously read from CE0, with each read being a 16-bit operation. When the external input IO signal triggers a high level, the system enters the interrupt service routine (ISR). The ISR (with priority level 0x16) first writes two 16-bit data items to CE1, and then reads one 16-bit data item from CE1.
During read operations, the interrupt trigger time is approximately 872 ns, which is reasonable. Additionally, there is no significant delay in processing CE0 data during chip select switching.
Expectation:
We want to avoid the situation shown in Figure 1, where the interrupt service routine and chip select switching still have to wait for ongoing CE0 data operations to complete. Since this interrupt is used to handle real-time data, what solutions can be applied to resolve this issue?
