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TDA4VM: CPSW2G: ECC Errors

Hasan Aarzoo
Intellectual 495 points
Part Number: TDA4VM


Tool/software:

Hi TI,

MCU_CPSW0 gives registers bits (TX_ECC_ERR_EN and RX_ECC_ERR_EN) to enable/disable transmission/reception of frames with ECC errors on Host Port (Port 0) and MAC Port (Port 1).

TRM says, "Either the RX_ECC_ERR_EN or theTX_ECC_ERR_EN bits must be set in the register to test packet CRC errors.". Are these bits only for testing ECC CRC errors?

Mac Port Ingress: 

An Ethernet packet received on CPSW2G from CANoe (imagine). If there is an ECC error on packet received, CRC will be invalid and packet will be dropped at MAC Port.

  1. What is the use case to set  CPSW_PN_CONTROL_REG;RX_ECC_ERR_EN bit  to 0/1 ?
  2. If set 0, means disabled. The packets received on MAC dropped due to ECC. How will MAC port recognize ECC drop on packet recived from CANoe?
  3. If set 1, means enable. The packets received on MAC dropped  was already dropped due to invalid CRC. How will it be recieved?
  4. If this packet is dropped (CPSW_PN_CONTROL_REG;RX_ECC_ERR_EN set to 0) due to ECC, which CPSW_STAT1 will be incremented? 

Host Port Ingress: 

  1. What is the use case to set  CPSW_P0_CONTROL_REG;RX_ECC_ERR_EN bit  to 0/1 ?

    How will the ECC error detected on a packet copied via Udma from OCRAM to Port 0 ?
  2. If this packet is dropped (CPSW_P0_CONTROL_REG;RX_ECC_ERR_EN set to 0) due to ECC, which CPSW_STAT0  will be incremented? 
  3. If this packet is not dropped (CPSW_P0_CONTROL_REG;RX_ECC_ERR_EN set to 1), will this packet on egress from MAC Port has invalid CRC? 

Looking forward to hearing back from you.

Best regards,
Hasan

  • 0
    TI__Prodigy 600 points

    Hasan,

    TX_ECC_ERR_EN and RX_ECC_ERR_EN are used only to generate and test errors in the CPSW memories. Packet headers are protected by ECC.  Packet data is protected by an internal Castignoli CRC that is sent through the CPSW with every packet.  On egress the correct port type of CRC is generated for the packet after the internal CRC is checked for correctness.  These two bits allow the CRC portion to be tested.  The header ECC is tested with the ECC aggregator.  These two MMR bits have nothing to do with packets that ingress with CRC errors.  If a packet has an internal CRC error, it will egress an Ethernet port with at least one byte of the packet CRC inverted to indicate the error to the other side.  A memory protect error should be given if there is an internal bit flip on packet data.  For ingress CRC errors, the packet will be dropped as usual (unless CEF is set to transfer error packets to the host).

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    Thank you for the response.

    Mark Bryans said:
    A memory protect error should be given if there is an internal bit flip on packet data

    Is this memory protect error statistics incremented for a single bit flip or for a multiple bit flip?

    Looking forward to hearing back from you.

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    Hasan,

    A memory protect error is detected by internal Castignoli CRC error - so any change in packet data should be detected.

       Mark

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    Mark Bryans said:
    Packet headers are protected by ECC. 

    If packet header experiences a single bit error, it will be auto corrected, this won't be considered an error and no statistics counter will be incremented in this scenario, right?

    If packet header experiences a double bit error, it will be an error and which statistics counter will be incremented?

    Looking forward to hearing back from you.

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    Hasan,

    A single bit error in a packet header will be corrected and will generate an SEC interrupt to the host.  A double bit error in the packet

    header will issues a DED interrupt to the host.  Double bit errors are not correctable and require a hardware reset.

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,


    Mark Bryans said:
    A single bit error in a packet header will be corrected and will generate an SEC interrupt to the host.

    Which STATS counter will increment for this, like CPSW_STAT1_MEMORY_PROTECT_ERROR, or any other?

    Mark Bryans said:

    A double bit error in the packet

    header will issues a DED interrupt to the host.

    Which STATS counter will increment for this, like CPSW_STAT1_MEMORY_PROTECT_ERROR, or any other?

    Looking forward to hearing back from you.

    Best regards,

    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    There is no stat for a SEC or DED error.  They are immediate interrupts.

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    Imagine an Ethernet packet is received on CPSW2G Mac Port (Port 1). The CRC and the destination MAC address is correct. The Ethernet packet inside CPSW2G is protected in two ways which are:

    1. Castignoli CRC on Packet data
    2. ECC protection on Packet header

    Based on my understanding and the discussion above, I can conclude the following:

    1. If there is/are a single bit flip/multiple bit flips on Packet data, it will be dropped at Host Port and CPSW_STAT0_TX_MEMORY_PROTECT_ERROR count is incremented.
    2. If there is a single bit flip on Packet data, it will be auto corrected. But if there are multiple bit flips, it will not be corrected. In both the cases, Ethernet packet will be dropped at Host Port and no CPSW STATS will be provided.

    Please let me know if my understanding is correct and if it is not correct, please correct it for me to have a better understanding of the concept.

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    2.  If there is a single bit flip on Packet HEADER, it will be auto corrected. But if there are multiple bit flips on packet HEADER it will not be corrected. In both the cases, Ethernet packet will be dropped at Host Port and no CPSW STATS will be provided.  SEC and DED interrupts will be issued.

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    Thank you for correcting my undersatnding.

    Again I have a question:

    Mark Bryans said:
    2.  If there is a single bit flip on Packet HEADER, it will be auto corrected. But if there are multiple bit flips on packet HEADER it will not be corrected. In both the cases, Ethernet packet will be dropped at Host Port and no CPSW STATS will be provided.  SEC and DED interrupts will be issued.

    When single bit error in packet header is auto corrected then why the packet is dropped at Host Port?

    Looking forward to hearing back from you.

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    Hasan,

    Apologies for the incorrect statement.  SEC errors are corrected with an issued interrupt (if enabled).  The packet is not dropped.  DED errors are detected with an issues interrupt (if enabled).  The packet is not dropped.

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    In both the cases (SEC and DED), the ethernet packet is not dropped and passed to Host Port. The CPSW2G only knows of the SEC and DED only if the interrupts are enabled. Do I need to check these interrupts with each packet received for SEC and DED?

    Best regards,

    Hasan  

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    Hasan,

    Your software should have the interrupts enabled so that if you receive an interrupt you know that there was the SEC or DED error.

    SEC errors will be corrected so there is nothing for software to do.  DED errors require hardware reset.

  • 0 in reply to Mark Bryans
    Intellectual 495 points

    Hi Mark,

    Any update on this.

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Prodigy 600 points

    Hasan,

    MEMORY_PROTECT_ERRORS should be dropped to the host in the 2port.  Is this what you are seeing?

    SEC errors are corrected.  DED errors will not be dropped and require a hardware reset.