AM68A: Changing u-boot console from UART8 to UART2

Hi Frank,

Can you follow the steps outlined here: (+) [FAQ] TDA4VM: J721e:/J7200: How to switch console to a different UART instance - Processors forum - Processors - TI E2E support forums

The device is different, but the steps should still apply.

Best,
Jared

In thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1490510/j784s4xevm-tda4ap-q1-changing-u-boot-console-from-uart8-to-uart3-no-clock-defined has been stated that the clock for the new UART have to be enabled. When I look into my u-boot sources it seems only UART5 & UART8 clocks are enabled. Should UART2 clock be enabled for our purpose as well?

Frank

Hi Frank,

If it is not already, yes.

Best,
Jared

Can you please point me to the description how I have to do it? Or is there a commit in u-boot which does it for another UART?

Frank

Hi Frank,

I've written a patch based off the changes Gokul made in the thread you linked: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1490510/j784s4xevm-tda4ap-q1-changing-u-boot-console-from-uart8-to-uart3-no-clock-defined 

The changes are essentially just adding the clock identifier and power domain for the UART2.

Magic values are taken from the ctrl mmrs, clock identifiers, and power domains. The ctrl mmr address can be found in the TRM, and the clock identifier and power domain can be found in the j721s2-main.dtsi.

Path file:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_arm_2D00_mach_2D00_k3_2D00_r5_2D00_data_2D00_Add_2D00_UART2_2D00_clock_2D00_and_2D00_dev_2D00_definiti.patch

Text:

From a0cd31e78227e798ebdd4e4a18ffff2b71a141f9 Mon Sep 17 00:00:00 2001
From: Jared McArthur <j-mcarthur@ti.com>
Date: Wed, 2 Jul 2025 11:48:17 -0500
Subject: [PATCH 1/1] arm: mach-k3: r5: *-data: Add UART2 clock and dev
 definitions

Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
---
 arch/arm/mach-k3/r5/j721s2/clk-data.c | 3 +++
 arch/arm/mach-k3/r5/j721s2/dev-data.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
index 0130c9c4b86..b8fab099350 100644
--- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
@@ -279,6 +279,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
 	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+	CLK_DIV("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0),
 	CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
 	CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
@@ -436,6 +437,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
+	DEV_CLK(351, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(351, 3, "usart_programmable_clock_divider_out2"),
 	DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"),
 	DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
index b78550707c5..b27c3fcb098 100644
--- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
@@ -69,6 +69,7 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(99, &soc_lpsc_list[12]),
 	PSC_DEV(98, &soc_lpsc_list[13]),
 	PSC_DEV(146, &soc_lpsc_list[14]),
+	PSC_DEV(351, &soc_lpsc_list[15]),
 	PSC_DEV(354, &soc_lpsc_list[15]),
 	PSC_DEV(357, &soc_lpsc_list[15]),
 	PSC_DEV(4, &soc_lpsc_list[16]),
-- 
2.34.1

Best,
Jared

Thank you very much! This seems to work for most of the u-boot part and the Linux kernel.

I still get output on UART8 from very first u-boot stage (R5 part?), ATF and OPTEE. Changing the ATF configuration (K3_USART) and/or OPTEE configuration (CFG_CONSOLE_UART) from 8 to 2 leads to non-booting system.

Frank

Hi Frank,

Can you send the patch of the changes you made, so I can go over it?

Best,
Jared

u-boot release is 10.00.00.08 and we applied your patch.

In devicetree we have

/ {
    chosen {
        stdout-path = "serial2:115200n8";
    };

    aliases {
        serial0 = &wkup_uart0;
        serial1 = &mcu_uart0;
        serial2 = &main_uart2;
    };

...

};

And in devicetree-u-boot.dtsi we enabled UART2

&main_uart2 {
    bootph-all;
};

and deleted the corresponding main_uart8 entry.

For OPTEE and ATF we have no patches just changed the uart configuration values (CFG_CONSOLE_UART & K3_USART) during build process.

Frank

Hi Frank,

Did you make the changes reflected in the FAQ: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/988278/faq-tda4vm-j721e-j7200-how-to-switch-console-to-a-different-uart-instance?

Best,
Jared