This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SRIO Different Result From C6670 and C6678

Hi,

I used below SRIO sample, run in C6670 and C6678, but result was different.

8171.SRIO_C6670_1.zip

C6670 result was fails.

C6678 result was pass.

CCS:V5.0.3

MCSDK:02_00_04_16

Thank You.

Best Regards.

  • I cannot tell the difference in your code that runs on C6670 v/s C6678.

    One key difference to keep in mind is the SRIO Serdes PLL configuration might be different. The C6678 EVM has a 312.5Mhz refclk and the C6670 EVM has a 250Mhz clock.  

    You can refer section 2.3.1.1. (Enabling PLL) :  

    http://www.ti.com/lit/ug/sprugw1a/sprugw1a.pdf

    Hope this helps.

  • Hi,

    Thank you for your reply.

    I want to change SRIO_SGMII_CLKP/N frequency to 312.5MHZ.

    I rewite below register value:

     

    CSL_BootCfgSetSRIOSERDESConfigPLL (0x229); 

    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495); 

    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);

    But SRIO connect have problem.

    Is this correct?

    Have any solution for this?

     

     

    Thank You.

    Best Regards.

     

  • Hello,

    Can you please confirm which EVM/board you are using for C6670 and C6678. 

    Assuming you are using Advantech EVMs,

     

    Please see the code snippet below for C6678. This is from MCSDK package :

    ..\pdk_C6678_1_1_0_0\packages\ti\transport\ipc\examples\srioIpcBenchmark\device_srio.c

     

        /* Assuming the ref_clock of 312.5 MHz and link rate is 5Gbps; program the PLL accordingly. */

        CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

     

    Our suggestion would be to first ensure the simple examples that come with MCSDK work fine. Then use them as reference for your customized application.

    Also - please give more details about what errors you are seeing.

     

    Hope this helps.

  • Hi,

    Thanks for your reply.

    I'm sure used C6670 and C6678 EVM plateform.

    When I initially C6670 and C6678 platforms SRIO interface switch can find C6678 device, but can't understand C6670 device.

    Switch SRIO reference frequence is 312.5MHZ,

    How can I change C6670 EVM SRIO reference frequence?

    Thank You

    best Regards,

  •  

    Hi,

    The EVM reference clock cannot be changed.

    For 6670 ref clock is 250Mhz. So for SRIO rate of 5GBps, PLL setting is 

        CSL_BootCfgSetSRIOSERDESConfigPLL (0x251);

    My reference is : MCSDK package file name :

    \pdk_C6670_1_1_0_0\packages\ti\transport\ipc\examples\srioIpcBenchmark\device_srio.c

     

    FYI :

    New MCSDK , version 2.0.5 is out. It maybe a good idea to download and use this.

    http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

     

    Hope this helps.

     

  • Hi,

    Can you please help us for the below queries ?

    I gone through the C6670 SRIO User guide and Example program " MulticoreLoopbackExample Project" .

    I have read in the user guide that we can control how Hardware segments the packet . (i.e) 8 Bytes to 256 Bytes. I hope it means that SRIO driver is capable segment the packet that that will be sent out.

    However I do not find any information in the example code or user guide about this segmentation information fields. Instead I saw the SRIO_MAX_MTU which was set as 256 Bytes in  ex program. This information was passed in CPPI Rx config , CPPI Tx config.

    Can you please tell us where to pass segment info in order to make driver to do the packet segmentation ?

    Thanks & Regards

    Rajkumar