Tool/software:
Hi,
I have a customized board based on EVM.
On EVM, MAC PORT 1,3,4,5 are configured as QSGMII, and connected to the ENET expansion board.
On this customized board, MAC PORT 8 is connected to a PHY 88M222x through SGMII.
I want to do a quick fix, so I didn't create a new board, but to reuse j784s4evm as much as possible.
I read through the porting guide, this is the corresponding modification:
1. Ethernet port interface type selection
--- a/pdk_j784s4_09_00_01_04/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
+++ b/pdk_j784s4_09_00_01_04/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
@@ -237,19 +237,25 @@ static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,
static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
{
Board_STATUS status = BOARD_SOK;
uint8_t portNum;
/* Configure the CPSW9G ENET1 QSGMII ports */
for(portNum = 0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
if ( 1U == portNum ||
5U == portNum ||
- 6U == portNum ||
- 7U == portNum )
+ 6U == portNum)
{
/* These ports are ununsed by default ENET1 board configuration */
continue;
}
+ else if (7U == portNum)
+ {
+ status = Board_cpsw9gMacModeConfig(portNum, SGMII);
+ }
else if (BOARD_CPSW9G_ENET1_QGMII_PORTNUM == portNum)
{
status = Board_cpsw9gMacModeConfig(portNum, QSGMII);
@@ -264,6 +270,7 @@ static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
return BOARD_FAIL;
}
}
return status;
}
2. Enabling modules via SciClient
used to enable CPSW9G module, so no need to change
3. Pinmux settings
MDIO/MDC pins, so no need to change
4. Ethernet PHY initialization
PHY reset pin is reset when powering up, so no need to change.
5. SerDes configuration
I reuse the EVM Board_CfgQsgmii, but set Sgmii instead.
--- a/pdk_j784s4_09_00_01_04/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c
+++ b/pdk_j784s4_09_00_01_04/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c
@@ -166,6 +166,9 @@ static Board_STATUS Board_CfgQsgmii(uint32_t boardID)
{
laneNum = BOARD_SERDES_SGMII_ENET1_LANE_NUM;
laneMask = BOARD_SERDES_SGMII_ENET1_LANE_MASK;
+^M
+ laneNum = BOARD_SERDES_SGMII_ENET2_LANE_NUM;^M
+ laneMask = BOARD_SERDES_SGMII_ENET2_LANE_MASK;^M
}
else
{
@@ -180,14 +183,14 @@ static Board_STATUS Board_CfgQsgmii(uint32_t boardID)
serdesLaneEnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;
serdesLaneEnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLaneEnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
- serdesLaneEnableParams.linkRate = CSL_SERDES_LINK_RATE_5G;
+ serdesLaneEnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;^M
serdesLaneEnableParams.numLanes = 1U;
serdesLaneEnableParams.laneMask = laneMask;
serdesLaneEnableParams.SSC_mode = CSL_SERDES_NO_SSC;
- serdesLaneEnableParams.phyType = CSL_SERDES_PHY_TYPE_QSGMII;
+ serdesLaneEnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;^M
serdesLaneEnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLaneEnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;
- serdesLaneEnableParams.pcieGenType = CSL_SERDES_PCIE_GEN4;
+ serdesLaneEnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;^M
serdesLaneEnableParams.laneCtrlRate[laneNum] = CSL_SERDES_LANE_FULL_RATE;
serdesLaneEnableParams.loopbackMode[laneNum] = CSL_SERDES_LOOPBACK_DISABLED;
6. CPSW clocks configuration
no change.
7. MAC address pool
no change.
8. MAC port and PHY configuration
--- a/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
+++ b/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
@@ -238,6 +238,20 @@ static EthFwBoard_MacPortCfg gEthFw_qenetMacPortCfg[] =
.sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
.linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
},
+ { /* "P3" */
+ .macPort = ENET_MAC_PORT_8,
+ .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
+ .phyCfg =
+ {
+ .phyAddr = 1U,
+ .isStrapped = false,
+ .skipExtendedCfg = false,
+ .extendedCfg = NULL,
+ .extendedCfgSize = 0U,
+ },
+ .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
+ .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+ },
};
diff --git a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
index bbdfd642..a9aad949 100644
--- a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+++ b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
@@ -150,6 +150,7 @@ static Enet_MacPort gEthAppPorts[] =
ENET_MAC_PORT_3, /* QSGMII sub */
ENET_MAC_PORT_4, /* QSGMII sub */
ENET_MAC_PORT_5, /* QSGMII sub */
+ ENET_MAC_PORT_8
#endif
};
@@ -158,19 +159,7 @@ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
{
.remoteCoreId = IPC_MPU1_0,
.portId = ETHREMOTECFG_SWITCH_PORT_0,
- },
- {
- .remoteCoreId = IPC_MCU2_1,
- .portId = ETHREMOTECFG_SWITCH_PORT_1,
- },
- {
- .remoteCoreId = IPC_MPU1_0,
- .portId = ETHREMOTECFG_MAC_PORT_1,
- },
- {
- .remoteCoreId = IPC_MCU2_1,
- .portId = ETHREMOTECFG_MAC_PORT_4,
- },
+ }
};
But the SERDES PLL is not locked
684.610592 s: Warning: Using 6 MAC address(es) from static pool 684.610732 s: ETHFW: Shared multicasts (software fanout): 684.610759 s: 01:00:5e:00:00:01 684.610781 s: 01:00:5e:00:00:fb 684.610801 s: 01:00:5e:00:00:fc 684.610820 s: 33:33:00:00:00:01 684.610840 s: 33:33:ff:1d:92:c2 684.610860 s: 01:80:c2:00:00:00 684.610879 s: 01:80:c2:00:00:03 684.610900 s: ETHFW: Reserved multicasts: 684.610917 s: 01:80:c2:00:00:0e 684.610936 s: 01:1b:19:00:00:00 684.611073 s: EnetMcm: CPSW_9G on MAIN NAVSS 684.622237 s: PHY 1 is alive 684.623510 s: CpswMacPort_setSgmiiInterface: MAC 8: SERDES PLL is not locked 684.623549 s: CpswMacPort_setSgmiiInterface: 684.623575 s: Assertion @ Line: 2287 in src/mod/cpsw_macport.c: false
Could you please give me some guidance? Thank you!
