SK-AM62A-LP: C7x performance is lower than C66x

O.H

Part Number: SK-AM62A-LP

Tool/software:

Hi experts,

My customer is using the AM62A evaluation board to evaluate C7x on nortos.
After booting with SBL NULL, our app is loaded on c7x via the debugger.
When I measured it, the performance was several times slower than 66AK.
(Based on the SBL NULL boot log, I assume it is running at 850MHz, but even so it is taking 4 to 5 times longer.)
It's not abnormally slow, but it's not as expected, so I'm looking for a way to improve it.

Q1:When booting c7x from SBL NULL, I understand that the cache is enabled by "c7x_startup_init()" in "kernel\nortos\dpl\c75\Startup.c". Is this correct? The API Reference doesn't seem to provide any details.
Q2:Also, is there a register to check if the cache is running on c7x?

Best regards,
O.H

3 months ago

0 O.H 3 months ago

Mastermind 6330 points

Hi experts,

Additional question.

Q3:Is it possible to run the PROC135E3 of SK-AM62A-LP at 1GHz?The marking is "XAM62A74AT", but will it automatically drop to 500MHz?

Q4:Is there a way to check the operating frequency?
Based on the SBL NULL log, I assume it is running at 850MHz.
Since the purpose is evaluation, I plan to use the correct model number (T grade or higher) for mass production.

Best regards,
O.H

0 O.H 3 months ago

Mastermind 6330 points

Hi experts,

Sorry for rush you. Is there any update?

Best regards,
O.H

+1 Shreyansh Anand 3 months ago in reply to O.H

TI__Expert 5720 points

Hi O.H,
Sorry for the delay in answering the questions.

O.H said:
Q1:When booting c7x from SBL NULL, I understand that the cache is enabled by "c7x_startup_init()" in "kernel\nortos\dpl\c75\Startup.c". Is this correct? The API Reference doesn't seem to provide any details.

Yes, your understanding is correct.

O.H said:
Q2:Also, is there a register to check if the cache is running on c7x?

There is L1DCFG register which you can look at, you will find more details about it in SPRUIQ3.

O.H said:
Q3:Is it possible to run the PROC135E3 of SK-AM62A-LP at 1GHz?The marking is "XAM62A74AT", but will it automatically drop to 500MHz?

I am not sure yet. I will get back to you asap on this.

O.H said:
Q4:Is there a way to check the operating frequency?

Please take a look at sciclient_get_version example in the SDK, it has a code block to fetch the CPU clock which uses Sciclient_pmGetModuleClkFreq(). You can modify the example slightly to get any core's clock.

Thanks,

Shreyansh

0 O.H 2 months ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Thank you for your reply.

Q1: I understood.

Q2: I did not have "SPRUIQ3", so I requested it from the link below. Please follow up on the approval if possible.
:www.ti.com/.../swlicexportcontrol.tsp

Q3: We look forward to receiving additional information.

Q4: I understood.

Best regards,
O.H

0 O.H 2 months ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Additional information.

When customer checked with the "PROC135E3" EVM, the result was indeed 850000000Hz.

[SCICLIENT] CPU clock frequency = 850000000 Hz

They are concerned about the difference with the bootloader setting and the consistency with the upper limit setting in speedgrade.

Q5: If the "PROC135E3" EVM can run at 1GHz, could you tell me if there is a way to set the c7x frequency at startup?

Best regards,
O.H

0 O.H 2 months ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Additional information.

A customer is reviewing the contents of DSPLIB regarding cache settings.
It seems that the cache settings are made by the DSPLIB_TEST_init function, and we have found that the performance results in about 1.5 to 2 times the number of cycles (slower) depending on whether or not the settings are made by this function.

Q6: Where can I get a manual that describes the register information used in this process, such as MAR and SCR? Is it written in "SPRUIQ3"?
We have been informed that it is correct to send a request for "SPRUIQ3(C7X-SW)" via the link below. We need the materials immediately, so we would appreciate it if you could follow up with your approval.
:https://www.ti.com/drr/opn/C7X-SW

Best regards,
O.H

0 Shreyansh Anand 2 months ago in reply to O.H

TI__Expert 5720 points

O.H said:
Where can I get a manual that describes the register information used in this process, such as MAR and SCR? Is it written in "SPRUIQ3"?

Hi O.H,
Yes, it is part of SPRUIQ3 doc. Your request has been approved.

Thanks,

Shreyansh

0 O.H 2 months ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Thank you for your support. I understand Q6 and Q2.

Please let me know the progress on the remaining Q3 and Q5.

Best regards,
O.H

0 O.H 2 months ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

I was able to get the documentation for "SPRUIQ3(C7X-SW)".

Sorry for rush you. Is there any update about Q3, Q5?

Best regards,
O.H

0 Krithika Ravi 2 months ago in reply to O.H

TI__Mastermind 20447 points

Hi O.H.,

O.H said:
Q3:Is it possible to run the PROC135E3 of SK-AM62A-LP at 1GHz?The marking is "XAM62A74AT", but will it automatically drop to 500MHz?

All silicon testing and Auto qualification of the devices are carried out for the specific speed grade that the device is rated for. So while technically the core can be run at a higher frequency than what it is rated for in the datasheet, this is not advisable to violate the datasheet. TI recommends staying at or below the speed grade in the datasheet in order for TI's quality assurance and guarantee to apply.
The core will not automatically drop to 500MHz, it will have to be set explicitly.

I will pass this thread to my colleague to answer Q5.

Regards,
Krithika

0 O.H 2 months ago in reply to Krithika Ravi

Mastermind 6330 points

Hi Krithika,

Sorry for late response. Thank you for your support.

I understood sbout Q3.

Any updates regarding the Q5 would be helpful for us.

Best regards,
O.H

+1 Shreyansh Anand 2 months ago in reply to O.H

TI__Expert 5720 points

Hi O.H,

Apologies for the late reply.
Please do the following changes in source\drivers\bootloader\soc\am62ax\bootloader_soc.c and rebuild the driver, sbl stage 2 and dm application.

From 4fa3af8d3f1b3ad653417c19af4bb1c3470be83b Mon Sep 17 00:00:00 2001
From: Anand <s-anand@ti.com>
Date: Wed, 16 Jul 2025 12:19:10 +0530
Subject: [PATCH 1/2] Enabled C7X CPU Clock modification

---
 bootloader_soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bootloader_soc.c b/bootloader_soc.c
index eaf28f1..8516b55 100644
--- a/bootloader_soc.c
+++ b/bootloader_soc.c
@@ -552,7 +552,7 @@ int32_t Bootloader_socCpuSetClock(uint32_t cpuId, uint32_t cpuHz)
     uint32_t sciclientCpuDevId;
     uint32_t sciclientCpuClkId;
 
-    if((cpuId != CSL_CORE_ID_HSM_M4FSS0_0) && (cpuId != CSL_CORE_ID_C75SS0_0))
+    if((cpuId != CSL_CORE_ID_HSM_M4FSS0_0))
     {
         sciclientCpuDevId = Bootloader_socGetSciclientCpuDevId(cpuId);
         sciclientCpuClkId = Bootloader_socGetSciclientCpuClkId(cpuId);
-- 
2.33.0.windows.2


From de16d9281c30f277355d6b4ff9e10874633dc244 Mon Sep 17 00:00:00 2001
From: Anand <s-anand@ti.com>
Date: Wed, 16 Jul 2025 12:30:51 +0530
Subject: [PATCH 2/2] Updated C7x clock to 1GHz

---
 bootloader_soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bootloader_soc.c b/bootloader_soc.c
index 8516b55..e943c39 100644
--- a/bootloader_soc.c
+++ b/bootloader_soc.c
@@ -163,7 +163,7 @@ Bootloader_CoreBootInfo gCoreBootInfo[] =
     .tisciProcId    = SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0,
     .tisciDevId     = TISCI_DEV_C7X256V0_C7XV_CORE_0,
     .tisciClockId   = TISCI_DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK,
-    .defaultClockHz = (uint32_t)(500*1000000),
+    .defaultClockHz = (uint32_t)(1000*1000000),
     .coreName       = "c7x0-0",
     },
 };
-- 
2.33.0.windows.2

Thanks,

Shreyansh

0 O.H 1 month ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Thank you for your reply. I understand the changes.

Regarding the part about "rebuilding the driver, sbl stage 2, and dm application", specifically which builds in the mcu plus sdk are you referring to?
If possible, I would like to check the startup with sbl null that reflects the changes.

Best regards,
O.H

+1 Shreyansh Anand 1 month ago in reply to O.H

TI__Expert 5720 points

Hi O.H,

You can rebuild the libs using:

make -s libs PROFILE=debug

Then rebuild your SBL application, and dm application that your are going to flash. Otherwise, you can even rebuild the entire MCU PLUS SDK to avoid confusion:

make -s  all PROFILE=debug

Thanks,

Shreyansh

0 O.H 1 month ago in reply to Shreyansh Anand

Mastermind 6330 points

Hi Shreyansh,

Thank you for your support. We were able to change the frequency using your method.

Best regrads,
O.H

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SK-AM62A-LP: C7x performance is lower than C66x