[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Custom board hardware design - Updates to Hardware Design Considerations and Schematic Design Guidelines collaterals

Hi Board Designers,

Refer below:

Processor product page 

AM64x

The processor product page links on TI.com are listed below:

https://www.ti.com/product/AM6442

AM64x (ALV)
• AM6442
• AM6441
• AM6422
• AM6421
• AM6412
• AM6411
AM243x [ALV, ALX]
• AM2434
• AM2432
• AM2431

AM62Lx (ANB)

The processor product page links on TI.com are listed below:

ti.com/product/AM62L

AM62L

AM62x (ALW, AMC, AMK)

The processor product page links on TI.com are listed below:

https://www.ti.com/product/AM625

• AM625 (ALW package)
• AM623 (ALW package)
• AM620-Q1 (AMC package)
• AM625-Q1 (AMC package)
• AM625SIP (AMK package)

AM62A

The processor product page links on TI.com are listed below:

https://www.ti.com/product/AM62A7

AM62Ax (AMB, ANF)
• AM62A7
• AM62A7-Q1
• AM62A3
• AM62A3-Q1
• AM62A1-Q1
AM62D-Q1 (ANF)
• AM62D-Q1

AM62P (AMH)

The processor product page links on TI.com are listed below:

https://www.ti.com/product/AM62P

• AM62P
• AM62P-Q1

Hardware design considerations current revision on TI.com

AM64x 

Hardware Design Guide
https://www.ti.com/lit/pdf/sprad67

sprad67b.pdf

AM62L

Hardware Design Considerations
https://www.ti.com/lit/pdf/SPRUJC9

AM62x

Hardware Design Considerations
https://www.ti.com/lit/pdf/sprad05

sprad05c.pdf

AM62A

Hardware Design Considerations
https://www.ti.com/lit/pdf/sprad85

sprad85b.pdf

AM62P 

Hardware Design Considerations
https://www.ti.com/lit/pdf/sprada9

sprada9a

Updates to sprada9a

Update 1:

Current 

7.8 Display Subsystem (DSS)
The processor family supports Open LVDS

OLDI0 display interface:
The processor family supports x4 (four) data lanes and x1 (single) clock lane, x2 (dual) link LVDS OLDI display
interface. OLDI0 interface can be configured for x2 OLDI-SL single-link or x1 OLDI-DL dual-link display mode.

When OLDI0 display interface is configured for dual-link display mode, there are "Odd/Even" requirements (for
pixels). A0, A1, A2, A3 correspond to Odd pixels and A4, A5, A6, A7 correspond to the Even pixels.

When OLDI0 interface is configured for x2 single-link display mode, the OLDI0 interface supports (can be
configured) only mirrored (duplicate, due to internal hardware support/configuration) mode.

Required to be updated to

7.8 Display Subsystem (DSS)
The processor family supports Open LVDS

OLDI0 display interface:

The processor family supports configuring the OLDI display interface for x2 OLDI-SL single-link (x4 (four) data lanes and x1 (single) clock lane) or x1 OLDI-DL dual-link  The processor family supports configuring the OLDI display interface for x2 OLDI-SL single-link (x4 (four) data lanes and x1 (single) clock lane) or x1 OLDI-DL dual-link  (x8 (eight) data lanes and x2 (dual) clock lane) display mode. For OLDI-DL dual-link A0 through A3 correspond to the ODD pixels and A4 through A7 correspond to the even pairs.

 When OLDI0 display interface is configured for dual-link display mode, there are "Odd/Even" requirements (for pixels). A0, A1, A2, A3 correspond to Odd pixels and A4, A5, A6, A7 correspond to the Even pixels.

When OLDI0 interface is configured for x2 OLDI-SL single-link display mode, the OLDI0 interface supports (can be configured) independent display streams (non-duplicate mode, non-mirrored mode).

Note: The Hardware Design Considerations User's Guide has been updated on TI.com. Review the FAQ and TI.com processor specific product page to updates.

Schematic Design Guidelines and Schematic Review Checklist

The FAQ is being updated. 

Regards,

Sreenivasa