AM5716: How to pass data from the A15 to the M4

I've read the above but I'm afraid that I am none the wiser - I have inherited an application that runs on the M4 & the A15, but neither use TI-RTOS, so the IPC is not available to me. This is a pity as the purpose of the IPC seems to be to hide the use of registers & bits & the memory map to simplify how to code this. The app uses etKernel for an RTOS on the A15, and a homegrown OS called V7MRTM on the M4.  My app defines 4 blocks of RAM that are unidirectional buffers to carry messages from the A15 to the M4 & back, and also from the A15 to the DSP & back. I think that the L4_CFG table defines the cross bar mapping of interrupt vectors to peripherals (which hopefully includes these blocks of memory). I am hoping that there is a bit in a register for each of these blocks that gets set when the data in the block is overwritten with new data, and that this causes an interrupt to the destination processor, and that this bit is then cleared by the destination processor when it reads the new data.

Am I on the right track with this more basic means of handling interprocessor comms between the processors? 

Hello,

I am out of office today. Please expect a 1-2 business day delay in response.

-Josue

Ken,

Using a different RTOS and HLOS other than Linux is not under the scope of this forum. There is a lot of information within our SDK that can be helpful. See 

• https://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#ipc-user-s-guide
• https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components_IPC.html#overview

Otherwise I suggest you reach out to the SW vendor for support: https://www.esol.com/embedded/services/support_top.php

software-dl.ti.com/.../Overview_Technical_Support.html

-Josue