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PROCESSOR-SDK-J784S4: UBOOT R5/A72 SPL Memory Usage

Jonas Mohrs
Prodigy 200 points
Part Number: PROCESSOR-SDK-J784S4

Tool/software:

Hello,

I have some questions related to the memory usage of the UBOOT R5 SPL and the UBOOT A72 SPL.

When I build the U-Boot R5 SPL and I check the corresponding map file, I find the start address 0x0000000080800000. According to the technical Reference Manual this would be the DDR memory range is that correct?


If yes, could you tell me which code part is initializing the DDR before the UBOOT R5 SPL is running?

Also in the linker file for the UBOOT A72 SPL I see the following definitions in the linker script:

MEMORY { .sram : ORIGIN = 0x80080000

Is that address really located in the SRAM? Where can I see that in the rechnical reference manual?

Thank you very much in advance.

  • 0
    TI__Guru** 111365 points

    Hi Jonas,

    R5 SPL does not run out of DDR. It is the bootloader component that initializes the DDR.

    Jonas Mohrs said:
    If yes, could you tell me which code part is initializing the DDR before the UBOOT R5 SPL is running?

    The R5 SPL itself is loaded and executed from the MCU SRAM. Following is the memory layout used by the initial MCU R5F bootloader components.

    Jonas Mohrs said:
    When I build the U-Boot R5 SPL and I check the corresponding map file, I find the start address 0x0000000080800000.

    This is typically the address that A72 SPL is loaded at and ATF uses to jump to.  Please note that the U-Boot bootloader binaries are typically position independent executables (PIEs), so it depends on where you link them against.

    Jonas Mohrs said:
    According to the technical Reference Manual this would be the DDR memory range is that correct?

    Correct.

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 200 points

    Hi,

    are you sure about that? The only PIE I saw was ATF BL31 everything else does not seem to be position independent.

    Thank you in advance.

  • 0 in reply to Suman Anna
    Prodigy 200 points

    Could you please also check why the linker scripts declares this address as sram:

    MEMORY { .sram : ORIGIN = 0x80080000,

    as written on top.

    Thank you in advance.

  • 0 in reply to Jonas Mohrs
    TI__Guru** 111365 points

    Hi Jonas,

    Jonas Mohrs said:
    are you sure about that? The only PIE I saw was ATF BL31 everything else does not seem to be position independent.

    The U-Boot linker command files are generated files that leverage the symbol definitions used in the defconfig files. The images themselves are raw binary images in the end, but these are converted through some image formatting commands like mkimage etc, which use arguments.

    This is not that much different from what is being done with ATF and OPTEE. So, you can probably call them pseudo position independent technically speaking because of the inherent U-Boot build automation flows. 

    Jonas Mohrs said:
    MEMORY { .sram : ORIGIN = 0x80080000,

    What file(s) are you looking at? This is the A72 SPL address.

    Following are the files when you build U-Boot from the top-level SDK on 11.0 SDK,

    R5 SPL: <ti-processor-sdk-linux-adas-j784s4-evm-11_00_00_08>/board-support/ti-u-boot-2025.01+git/build/r5/spl/u-boot-spl.lds

    A72 SPL: <ti-processor-sdk-linux-adas-j784s4-evm-11_00_00_08>/board-support/ti-u-boot-2025.01+git/build/a72/spl/u-boot-spl.lds

    The .sram ORIGIN addresses come from CONFIG_SPL_TEXT_BASE variables.

    $ cd <ti-processor-sdk-linux-adas-j784s4-evm-11_00_00_08>/board-support/ti-u-boot-2025.01+git/configs

    $ git grep -n CONFIG_SPL_TEXT_BASE j784s4*

    j784s4_evm_a72_defconfig:17:CONFIG_SPL_TEXT_BASE=0x80080000

    j784s4_evm_r5_defconfig:24:CONFIG_SPL_TEXT_BASE=0x41c00000

    regards

    Suman