Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello TI Community,
We are currently planning a custom board using the DRA829V processor and evaluating the SERDES configuration. Our intended allocation is as follows:
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SERDES 0: PCIe x2
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SERDES 1: 2x SGMII
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SERDES 2: USB 3
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SERDES 3: PCIe x1 + USB 3
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SERDES 4: DisplayPort + 3x SGMII
According to the SysConfig Tool, this configuration appears to be valid and supported. The TRM also describes these combinations as possible.
However, we came across older forum posts from around 5 years ago stating that some combinations—especially on SERDES 3 and 4—were not yet supported by the software stack at that time.
We would like to confirm whether the current SDK and software stack fully support this configuration.
Additionally, can the DRA829V generate all required SERDES reference clocks internally, or will external reference clocks be necessary for this configuration?
Any guidance or clarification would be highly appreciated.
Regards,
Lennart