TDA3XEVM: vout pixelclock control

Kim TaeJung

Part Number: TDA3XEVM

Tool/software:

vout

   if(displayType == CHAINS_DISPLAY_TYPE_LCD_7_INCH)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT;
        if ((BSP_PLATFORM_SOC_ID_TDA2EX == Bsp_platformGetSocId()) &&
            (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType()))
        {
            /* In case of TDA2EX and Package is 17 X 17, LCD is on DPI 3 */
            pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD3;
            pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI3_OUTPUT;
        }
        pVInfo->vencOutputInfo.vsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.hsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        pVInfo->mInfo.standard                  =   SYSTEM_STD_CUSTOM;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.scanFormat                =   SYSTEM_SF_PROGRESSIVE;
        pVInfo->mInfo.pixelClock                =   29232u;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hFrontPorch               =   40u;
        pVInfo->mInfo.hBackPorch                =   40u;
        pVInfo->mInfo.hSyncLen                  =   48u;
        pVInfo->mInfo.vFrontPorch               =   13u;
        pVInfo->mInfo.vBackPorch                =   29u;
        pVInfo->mInfo.vSyncLen                  =   3u;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        if(Bsp_platformIsTda3xxFamilyBuild())
        {
            pVInfo->vencDivisorInfo.divisorPCD      =   1;
        }
        else
        {
            pVInfo->vencDivisorInfo.divisorPCD      =   4;
        }

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                       = SYSTEM_DCTRL_DSS_VENC_LCD1;
        if ((BSP_PLATFORM_SOC_ID_TDA2EX == Bsp_platformGetSocId()) &&
            (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType()))
        {
            /* In case of TDA2EX and Package is 17 X 17, LCD is on DPI 3 */
            ovlyPrms->vencId                    = SYSTEM_DCTRL_DSS_VENC_LCD3;
        }
    }

I set the display type as above to set the vout pixelclock.

After the update, 149mhz is observed when measuring the vout clock.

It seems that the above setting is not reflected.

3 months ago

0 Brijesh Jadav 3 months ago

TI__Guru**** 476595 points

Hi Kim,

I think pixel clock in mode information is not really used. Can you please in the same file, where it is setting pixel clock? You would need to change in that API.

Regards,

Brijesh

0 Kim TaeJung 3 months ago in reply to Brijesh Jadav

Intellectual 620 points

The check result states that only 149, 74.5 are supported in opp_high mode.

Is there a way to change pixelclock in opp_high mode?

Regards,

Kim

0 Brijesh Jadav 3 months ago in reply to Kim TaeJung

TI__Guru**** 476595 points

Hi Kim,

Are you using Ethernet on TDA3x? If not, there is an option, otherwise, its not possible.

Regards,

Brijesh

0 Kim TaeJung 3 months ago in reply to Brijesh Jadav

Intellectual 620 points

Don't using Eternet on TDA3x

Regards,

Kim

+1 Brijesh Jadav 3 months ago in reply to Kim TaeJung

TI__Guru**** 476595 points

Hi Kim,

In Vision SDKJ3.8 release, we support DSP at 1GH and EVE at 900MHz frequency in opp_high. This configuration uses two DPLLs, GMAC PLL is used to get 1GHz for the DSP and DSP_EVE PLL is used to get 900MHz for the EVE.

Please find below configuration used in vision sdk 3.8 release

GMAC_PLL

M = 250, N = 4, M3 = 2, which gives 1GHz output for DSP on CLKOUTX2_M3 output of GMAC PLL.

DSP_EVE_PLL

M = 225, N = 4, M2 = 2, which gives 900Mhz for EVE on CLKOUTX2_M2 output.

But there is a limitation with this configuration. Video pixel clock is also sourced from DSP_EVE_PLL, which uses same M2 output. It means Video pixel clock can be 900MHz, 450MHz or 225MHz. None of these pixels clocks can be supported in the DSS, as they are too high

We can use GMAC_PLL to get 1GHz output for DSP and also 666MHz for EVE, ie from the same PLL, we can get both DSP and EVE's clock. and then we can use DSP_EVE_PLL to get pixel clock for the display.

In order to use this mechanism, we need to change SBL in the vision sdk 3.8 releese. SBL use API SBLUtilsConfigureDspEveMux to select the parent clock for the DSP and EVEM. This API is implemented in the file pdk_01_10_02_07\packages\ti\boot\sbl_auto\sbl_utils\src\tda3xx\sbl_utils_tda3xx.c. As we can see in this API, the parent for the DSP is selected as the GMAC clock and parent for the EVE is selected as DSP_EVE clock. We need to change here to use GMAC clock also for the EVE, as shown below.

#if (SBL_LIB_CONFIG_DSP_1000GHZ_EVE_900MHZ == (1U))
switch (oppId)
{
case SBLLIB_PRCM_DPLL_OPP_HIGH:
//retVal += PMHALCMMuxParentSelect(PMHAL_PRCM_MUX_EVE_CLK_MUX,
//PMHAL_PRCM_DPLL_EVE_VID_DSP);
/* Select EVE Clock Source */
retVal += PMHALCMMuxParentSelect(PMHAL_PRCM_MUX_EVE_GCLK_MUX,
PMHAL_PRCM_DPLL_DSP_GMAC);
retVal += PMHALCMMuxParentSelect(PMHAL_PRCM_MUX_EVE_CLK_MUX,
PMHAL_PRCM_MUX_EVE_GCLK_MUX);
break;
default:
/* Select EVE Clock Source */
retVal += PMHALCMMuxParentSelect(PMHAL_PRCM_MUX_EVE_GCLK_MUX,
PMHAL_PRCM_DPLL_DSP_GMAC);
retVal += PMHALCMMuxParentSelect(PMHAL_PRCM_MUX_EVE_CLK_MUX,
PMHAL_PRCM_MUX_EVE_GCLK_MUX);
break;
}
#else

Then we can change the values of multiplier and divisors to get the correct clock. This can be done in the file pdk_01_10_02_07\packages\ti\boot\sbl_auto\sbl_lib\src\tda3xx\sbl_lib_tda3xx_prcm_dpll.c

The structure instance dpllGmac15X15CfgOppHigh_20 is used to configure GMAC PLL and dpllGmac15X15PostDivCfgOppHigh_20 is used to configure divisors in opp_high. We need to change dpllGmac15X15PostDivCfgOppHigh_20 to get 666MHz EVE by changing post divisor H13 value to 2.

Can you please try these changes ?

Regards,

Brijesh

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TDA3XEVM: vout pixelclock control