Tool/software:
Hi,
My customer is asking for signal skew between below signals.
Do we have such data available?
1) CK and ADDR_CTRL
2) CK and DQS
3) DQS and DQ
Thanks and regards,
Koichiro Tashiro
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Tool/software:
Hi,
My customer is asking for signal skew between below signals.
Do we have such data available?
1) CK and ADDR_CTRL
2) CK and DQS
3) DQS and DQ
Thanks and regards,
Koichiro Tashiro
Hi James,
do you mean the signal skew from our EVMs?
No. The customer is asking signal timing differences at device pads.
Thanks and regards,
Koichiro Tashiro
Sorry, i don't understand what you are asking. Maybe they are they looking for package delays? This is in the DDR layout guidelines: https://www.ti.com/lit/pdf/sprad06 in section 5
Regards,
James
Hi James,
What the customer wants to know is below parameters.
a) CMD/ADD/CTRL signal delay(min/max) against CLK signal
b) DQS signal delay(min/max) against CLK signal
c) DQ signal delay(min/max) against DQS signal
The background of the question is;
The customer thinks total delay consist of (delay of PCB) + (package delay) + (above parameters a/b/c)
Thanks and regards,
Koichiro Tashiro
The signal delays are optimized during training and will most likely be different with every initialization cycle. The hardware training algorithms will adjust the relative skews of the signals for optimal timing. As long as you provide the correct DDR configuration using the DDR Register Configuration tool, https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62x, the controller/PHY training procedure will generate optimal skews across the signals in question. Signal delay values that are applied as calculated during training are only available as encoded values and do not represent anything the customer can use.
Regards,
James