Other Parts Discussed in Thread: AM62P
Tool/software:
Hi everyone,
I'm working with the SK-AM62P-LP development kit and have successfully tested the IMX219 camera using the provided "k3-am62x-sk-csi2-imx219.dtso" overlay.
Now, I'm trying to integrate an FPGA acting as a CSI-2 Transmitter (Tx) core with the AM62P's CSI-2 Receiver (Rx) interface. My goal is to receive video data from the FPGA at a resolution of 2560x1024, 24 bits per pixel (bpp), and 50 frames per second (fps).
I understand that this requires specific device tree modifications and potentially kernel configurations. I've been looking at existing camera overlays for guidance, but adapting them for a custom FPGA CSI-2 Tx (which might not have an I2C control interface like a standard sensor) is proving challenging.
Could anyone provide detailed guidance on the necessary device tree modifications and/or kernel configurations for this setup?
Specifically, I'm looking for:
- Device Tree Overlay (
.dtso
) example: A template or detailed explanation for a device tree node that describes a "virtual" sensor representing the FPGA's CSI-2 Tx, connecting it to the AM62P's CSI-2 Rx. This should include properties for resolution, pixel format (24bpp, likely RGB888 or similar), and ideally, information about using all 4 CSI-2 data lanes. - Relevant Kernel Configurations: Any specific kernel options (e.g.,
CONFIG_VIDEO_CADENCE_CSI2RX
) that need to be enabled or verified for the CSI-2 receiver to function correctly with a custom source. - Data Rate Considerations: Confirmation that 2560x1024 @ 50fps at 24bpp (approx. 3.145 Gbps) can be handled by the AM62P's 4-lane CSI-2 Rx, and if there are any specific settings or limitations to be aware of.
Additionally, if my FPGA CSI-2 Tx IP core has limitations that prevent it from supporting the full 2560x1024 resolution in a single stream, could you suggest an alternative method to receive this as two camera data streams (e.g., two 1280x1024 streams)? I'm particularly interested in how this would be handled on the AM62P side, considering it typically has a single CSI-2 Rx controller. Would this involve MIPI CSI-2 Virtual Channels from the FPGA, and how would that be reflected in the device tree and V4L2 framework?
Any insights, code snippets, or pointers to relevant documentation would be greatly appreciated!
Thank you in advance!