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AM6442: uart baud rate selection with sysConfig

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello.

I want to set the UART baud rate of USART1 to 5 Mbaud. According to table 12-470 in TRM this should be possible by using a clock source of 160MHz, a divider of 1 and the baud multiple set to x16. I am using SysConfig (1.14.0+2667) to configure the processor. With the mentioned parameters I get an error:

 I played around a bit and came up with the following setting:

With these parameters I see uart communication (measured with oscilloscope) with 5Mbaud. That's fine, but from the documentation I can not understand why these values result in a baud rate of 5M. Somehow it feels not right. I found these drawings in the TRM:

  

Can you give me some more insights how calculations are done? Thanks in advance.

BR Michael

  •  I played around a bit and came up with the following setting:

    Did you mean to say that with the above configurations you are seeing a baud rate of 5000000 on the waveform?

    Regards,

    Vaibhav

  • Yes exactly. I took a shot of the RX (and TX) signal(s). The duration of a bit is 200ns. The uart is connected to an FPGA. Communication between Sitara and FPGA works fine @5MHz.

  • So, the thing is that you set a frequency of 80 MHz and a baud rate of 3 MHz, but baud rate came out to be 5 MHz. This is strange behaviour.

    Let us dive step by step.

    Please check your application and the function where we call: System_init() -> Module_clockSetFrequency()

    Inside this, there will be a point where we set the frequency of UART, can you check if the UART's frequency of 80 MHz is set up properly?

    Regards,

    Vaibhav

  • The automatically generated file ti_power_clock_config.c contains the struct shown below which is used by Module_clockSetFrequency():
    SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {

        ...
        { TISCI_DEV_UART1, TISCI_DEV_UART1_FCLK_CLK, 80000000 },
        ...
        { SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
    };
  • Hi,

    By looking at the clock tree tool for AM64x, I see that a frequency of 80 MHz is possible with the following combination as shown in the diagram below.

    I am assuming the clock is setup correctly for your flow.

    Now coming to Clock Divider value, can you help me out with the same.

    You would need to head to the API call UART_configInstance and put a breakpoint at:

    /* Computing the Divisor Value for params.baudRate */
    divisorVal = UART_divisorValCompute(hUartInit->inputClkFreq,
    hUartInit->baudRate,
    hUartInit->operMode,
    UART_MIR_OVERSAMPLING_RATE_42);

    Please share with me the divisorVal computed from this.

    Regards,

    Vaibhav


  • hUartInit->operMode,

    Hi,

    the code lines in UART_configInstance (uart_v0.c) look a bit different. I am using mcu_plus_sdk_am64x_08_01_00_36:

        /* Computing the Divisor Value for params.baudRate */
        divisorVal = UART_divisorValCompute(attrs->inputClkFreq,
                                           prms->baudRate,
                                           prms->operMode,
                                           UART_MIR_OVERSAMPLING_RATE_42);
    attrs->inputClkFreq = 48000000
    prms->baudRate = 3000000
    prms->operMode = 0 (UART_OPER_MODE_16X)
    divisorVal = 1
    Strange that the inputClkFreq is set to 48000000.
    BR
  • Strange that the inputClkFreq is set to 48000000.

    So this is what I wanted to make sure. Looks like a basic SDK bug which was taken care of in the later releases.

    I am using mcu_plus_sdk_am64x_08_01_00_36:

    Any reason to stick to the older release, there has been many bug fixes since 8.1. Please see the release notes: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/11_00_00_15/exports/docs/api_guide_am64x/RELEASE_NOTES_PAGE.html

    Regards,

    Vaibhav

  • We'll update sdk version in the near future. So no need to stick to that older version. It's important to know that our settings for the UART are within the specification. I understand that the configuration with sysConfig is confusing due to an SDK bug which is solved in more recent versions, but the actual settings derived from .syscfg file are valid. Could you please confirm? Thanks a lot for your help.

  • Hi,

    Let me try something on my setup first.

    Please tell me if this is how you are measuring the baud rate:

    To measure the UART baud rate from a waveform, you need to determine the duration of a single bit and then calculate the baud rate as the inverse of that durationSpecifically, measure the time between two consecutive transitions (rising to falling or falling to rising) on the UART's transmit (TX) line. The baud rate is then 1 divided by this measured time

    Note, the above snippet is not from my logic analyzer, but an online image.

    Regards,

    Vaibhav

  • That's exactly how I determine the baud rate.

  • Thank you, I will put your configurations into one of the latest release and check if I see the same baud rate as well or not.

  • Hi,

    I have connected the logic analyzer to the UART2 TXD and seen the waveform as following:

    If you read closely, it sends the following string: "This is uart echo test blocking mode\r\nReceives 8 characters then echo's back. Please input.."

    I am going to measure the baudrate now and check if it is by default 115200 and then post this I will give your configurations and check if mismatch in baud rate is seen or not.

    Thanks for your patience.

    Vaibhav

  • Hi,

    Just a quick UPDATE:

    For the sample application where 115200 is configured, I see the baud rate of 115,207.37 on the waveform which is okay.

    Now moving onto your configuration:

    Please tell me what will be the baud rate based on the diagram below?

    I have made some changes which reflect the settings of 16x, baud rate: 3000000 and frequency: 80 MHz. From the above diagram please let me know what will be the baud rate, if you need further pointers do let me know as well.

    Looking forward to your response.

    Regards,

    Vaibhav