Tool/software:
OMAPL138BGWTMEP boots from Micron NAND Flash MT29F4G16ABBDAH4AIT on our circuit boards.
4096 blocks
64 pager per block
4 regions per page
512 bytes per region
We are using the 4-bit ECC feature of the EMIFA.
Regarding scenarios in which there are 1 to 4 single-bit errors total in a combination of the following for a region of a page:
512 data bytes
10 ECC parity bytes
What limits are expected for the computed address of the error word?
Reference:
OMAP-L138
C6000 DSP+ARM Processor
Technical Reference Manual
SPRUH77C
April 2013– Revised September 2016
20.2.5.6.6.2 4-Bit ECC
page 884
For reads:
...
14. Read the error address from the NAND Flash error address 1-2 registers (NANDERRADD[2:1]).
Address for the error word is equal to (total_words_read + 7 - address_value). For 518 bytes, the
address will be equal to (525 - address_value).
For each bit error in a 512 data byte region of a page, the computed address will lie in the range 0 to 511.
For each bit error in the ECC parity bytes, what is expected for the computed address?
Experimentally, I observe computed addresses in the range 515 to 518. Maybe 512 to 518, but I need to check that again.
The spare bytes (test bytes and ECC parity bytes) are not included in the ECC calculations.
I conclude the computed address and correction value cannot be used to locate and correct an error in the ECC parity data bytes.
Is it safe to assume a computed address in the range 512 to 518 indicates there is an error in the ECC parity data bytes and can be ignored? (Similar to the ROM Bootloader (RBL) patch described in Advisory 2.3.24 of the OMAP-L138 errata SPRZ301M)
Is it also safe to assume a computed address greater than 518 indicates an ECC failure and I should abort the read operation?