Hi,
We have developed a custom board based on DM3730 DSP processor. We are facing issue on bringing up 1024X600 res. 7'' LCD Manufacturer: CHIMEI INNOLUX (Model Name: AT070TNA2 V.1).
Our design has SN75LVDS83BDGGR interfaced to the parallel inputs from the processor. Please find the attached Schematic.
We are setting the input clock(DSS_PCLK) as 44 Mhz as per the LCD datasheet, though CLKIN (DSS_PCLK) shows correct frequency on scope 44Mhz, it shows the voltage swings between 650mV - 990mV (max 1.0V). As per the LVDS datasheet the input clock (CLKIN) should swing from 0.0 -1.8V ideally to see the correct clock on the output differential clock from the LVDS chip (CLKOUT pins of the chip). Please suggest us how to set the DM3730 Pixel clock to output from 0 to 1.8V.
We are not able to see the correct pictures on the LCD because the input clock is not matching the output clock.4745.LCDSchematic.pdf