TDA4VH-Q1: How to access 8MB central MSMC RAM from C71x code?

Hi,

Have you tried using 0x70000000 location to access this memory?

Regards,

Brijesh 

Thanks Brijesh for your response. 
Can you please elaborate and/or share an example so that I can understand better? Do you mean if I need to use the following pragma directive to access L3 mem when I use the linker file in ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/dsplib/cmake/linkers/C7120? 

#pragma DATA_SECTION (".neardata")

Please bear with me. 

Hi Ian,

No, i meant can you check L3 memory location in the memory map or in TRM, map this location in the MMU and then can you directly access them?

Regards,

Brijesh

Hi Brijesh, 

I'm sorry, I'm not experienced enough to implement your suggestion on my own. Would you mind sharing specific code changes based on your idea? It would be really helpful if you could demonstrate them using DSPLIB_add (dsplib/examples/DSPLIB_add/DSPLIB_add_examples.cpp) as I'm already familiar with that context from the original question.

Hi Ian Jeong,

Can you please refer to TRM, get the L3 memories address from TRM and try accessing it from C7x? I dont have sample code for the same. 

Regards,

Brijesh

Hi Brijesh,
I can give that a try. Please let me know the TRM that I can refer to if you already know it. I ask this because I have not yet found documents that provide memory addresses.

Hi Ian Jeong,

I already shared the L3 MSMC memory based address, 0x70000000, and TRM is available online.. So can you try accessing it? 

Regards,

Brijesh

Hi Brijesh. We could use a little more basic help on this topic, as the TRM is not very clear about the C7X memory map. At this stage in the development we are primarily focused on C7x programming using baremetal setup described in the RTOS SDK setup here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/10_01_00_04/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j784s4.html#debugging-without-hlos-running-on-a72-rtos-only-baremetal As such, we are not directly programming the MMU associated with the C7x, unless this is done by the debugging script.

Could you please point us to the specific pages in the TRM (www.ti.com/.../spruj52) where we can find the information about the C7x address range where the 8MB MSMC3 SRAM is mapped?

Does Table 2-1 memory map reflect the default address mapping from both the ARM and C7x perspective? 

Also does the 8MB MSMC3 SRAM map to the same address range for all four C7x DSPs, or are there aliased address ranges for each of the four C7X DSPs, as in the lower address ranges shown below? From experimentation with CCS I can see that there is SRAM at address 0x70000000 that is common between C71X_0 and C71X_1, etc. so I think the answer is yes, this is the same shared address for all four cores but please confirm, or better yet, please show us how to find/confirm this information ourselves.

Thanks