Our setup composed from FPGA (Altera ARRIA II GX) and DSP C6457. Our first board assembly route one SRIO lane (#0) between FPGA and DSP.
In that board we'd worked successfully with SRIO.
In our new board assembly all four SRIO lanes between FPGA and DSP are connected. We do succeed to work backward compatible on that board (1 lane configuration), but when trying to work with 4 lanes configuration we don't succeed (both sides) to initialize the port (SP0_ERR_STAT=1 i.e. port uninitialized).
In my DSP code I had followed the guidelines in the C6457 SRIO user guide (SPRUGK4D) regard changing from 1 to 4 lane configuration. I quote (p. 80)
" To change from 1 lane to 4 lanes there are 2 registers that need to be programmed (see Table 32).
Table 32. Port Mode Register Settings
SP_IP_MODE (offset 0x12004) PER_SET_CNTL (offset 0x0020)
Bits 31-30 (1) Bit 8 Port Mode
0x00 0x0 1x/4p(2)
0x01 0x1 1x/1x(3)
(1) Bits 31-30 are read only. To enable writing to read-only registers, change the PER_SET_CNTL register (offset 0020h) bit 24 to 0.
(2) UDI buffers are priority based.
(3) UDI buffers are port based.
Thus at my code I'd implement as followed :
data = hSrio->regs->PER_SET_CNTL;
#ifdef LANE_1
data = (0x0000014F & 0x000001FF) | (data & ~0x000001FF);
#else
data = (0x0000004F & 0x000001FF) | (data & ~0x000001FF);
#endif
hSrio->regs->PER_SET_CNTL =hSrio;
#ifdef LANE_1
pSetup->periCntlSetup.bufferMode = CSL_SRIO_1X_MODE_PORT; //=1
CSL_SRIO_1X_MODE_PRIORITY;
#else
pSetup->periCntlSetup.bufferMode = CSL_SRIO_1X_MODE_PRIORITY; //=0
#endif
#ifdef LANE_1
pSetup->portIpModeSet =0x4400003F; ;
#else
pSetup->portIpModeSet =0x0400003F;
#endif
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My questions
1) Is the fact that 1 configuration works on that board is enough to negate assembly problem (or physical problem) with the SRIO.
2) Does the inability to initialize the port could be relate to other processor functionality or port initialization doesn't involve with any negotiation with the other side( could be a situation where one side's port is initialized while other doesn't ?)
3) I can provide memory dump of SRIO registers if necessary
Best Regards
Yariv
