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AM3505 MPU DPLL

werner s
Prodigy 70 points

Dear forum,

I have a question about the MPU clock generation.

I measured 13MHz for CM_SYS_CLK at pin sys_clkout2. (AM35x Technical Reference Manual July 2010 sprugr0.pdf     page 230)

DPLL1_ALWON_FCLK should be the same as CM_SYS_CLK. (TRM page 228)

CM_CLKEN_PLL_MPU .EN_MPU_DPLL = 0x7 (DPLL1 lock mode)

Calculation using TRM page 232 for MPU clock = CLKOUT_M2X2 and values of registers:

(CLKSEL2_PLL_MPU[4:0], MPU_DPLL_CLKOUT_DIV):

M2 = 1

CM_CLKSEL1_PLL_MPU.MPU_DPLL_MULT:

M = 0x1F4 (=500) 

CM_CLKSEL1_PLL_MPU.MPU_DPLL_DIV:

N = 0x0C (=12)

CLKOUTX2 = (Fref x 2 x M) / (N+1):  (13Mhz * 2 * 500) / (12 + 1) = 1000MHz

MPU clock = CLKOUT_M2X2 = CLKOUTX2 / M2 = 1000MHz / 1 = 1000MHz


Is this the right frequency?

Shouldn't the maximum frequency of MPU clock be 500MHz?

 

Best regards,

Werner

 

 

 

 

 

 

 

 

  • 0
    TI__Genius 16690 points

    Yes, your settings are correct. ARM is running at ARM_FCLK which is generated by MPU clock generator in MPU Subsustem.  ARM_FCLK is a half of MPU_CLK frequency. Please refer to Figure 3-3. MPU Subsystem Clocking Scheme in the TRM (sprugr0b.pdf).