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DRA821U: CPSW time sync Event FIFO depths

Part Number: DRA821U

Tool/software:

Hi,

The TRM has the following for the single port MCU_CPSW:
12.2.1.4.7.8 Event FIFO
All time sync events are pushed onto the Event FIFO. There are 32 locations in the event FIFO with no overrun
indication supported. Software must service the event FIFO in a timely manner to prevent FIFO overrun.

And this for the multi-port main CPSW:
12.2.2.4.7.8 Event FIFO
All time sync events are pushed onto the Event FIFO. There are 10 locations in the event FIFO with no overrun
indication supported. Software must service the event FIFO in a timely manner to prevent FIFO overrun.

Is this a typo?

Rough calculations show that, in the absolute worst case, back-to-back PTP Delay_Req messages, spread over a possible one 10G and three 2.5G ports running concurrently in the main CPSW, could fill up a 10-deep Event FIFO in 418ns. 

Thanks,
Gerry