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C674x interrupt registers question.

Anatoly Odler
Expert 1870 points

Hello,

I'm working with OMAP - L138 with C6748 on it. No ARM is in the package. The IDE is CCSv5.

I have configured a GPIO pin to generate a bank interrupt. When I monitored the Core registers, I have noticed that IFR like never gets '1' in the proper position (the interrupt number I have assigned to my GPIO pin) and in addition the IER register gets '0' in the same appropriate position after the program gets into my ISR.

I have debugged the interrupt enabling issue, and everything looks fine when I enable/disable the interrupt by rotation.

Is it the IDE's bug? Or the Core just operates in such a way?

Thank you, Anatoly.