AM69: Direct Image Flashing to eMMC over USB from Host PC

Hi sun,

There is something called ums(USB mass storage) which can write an image directly to eMMC from HostPC.

These are the patches needed inorder to enable the UMS and fastboot functionality on TI J784S4 EVM.

1: https://serenity.dal.design.ti.com/patchwork/project/linux-patch-review/patch/20241001040449.3268386-1-s-vadapalli@ti.com/
2: https://serenity.dal.design.ti.com/patchwork/project/linux-patch-review/patch/20241008112833.1914173-1-s-vadapalli@ti.com/

3:

diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 3795bfe6b1c..2f77677427f 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -88,11 +88,13 @@
 };
 
 &usbss0 {
+       ti,usb2-only;
        bootph-pre-ram;
 };
 
 &usb0 {
        dr_mode = "peripheral";
+       maximum-speed = "high-speed";
        bootph-pre-ram;
 };
 
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 26a5e363862..79933dcaabb 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -194,3 +194,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_DFU=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_CMD_USB_MASS_STORAGE=y

Regards

Gokul

sorry for the late answer.

The links you show me seems like expired. I cannot reach to it.

So I can assume that the device should be ready for the USB write with the patches you shared.

Is there any needed procedure or documents about how to upload it?
I just need to plug my USB cable and then run dfu-utils?

Thanks.

Hi Minsoo,

I am attaching the patches shared in the above links since you are not able to access it . Can you ensure that the following patches have been applied ?

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index d11175dc5b6..7fa51d0fd70 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -965,6 +965,12 @@  int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
 	if (priv_dev->dev_ver <= DEV_VER_V2)
 		cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
 
+	/* Flush TRBs */
+	flush_dcache_range((unsigned long)priv_ep->trb_pool,
+			   (unsigned long)priv_ep->trb_pool +
+			   ROUND(sizeof(struct cdns3_trb) * priv_ep->num_trbs,
+				 CONFIG_SYS_CACHELINE_SIZE));
+
 	trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
 
 	/*
@@ -1153,6 +1159,13 @@  static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
 				priv_ep->endpoint.desc->bEndpointAddress);
 #endif
 
+		/* Invalidate TRBs */
+		invalidate_dcache_range((unsigned long)priv_ep->trb_pool,
+					(unsigned long)priv_ep->trb_pool +
+					ROUND(sizeof(struct cdns3_trb) *
+					      priv_ep->num_trbs,
+					      CONFIG_SYS_CACHELINE_SIZE));
+
 		if (!cdns3_request_handled(priv_ep, priv_req))
 			goto prepare_next_td;
 

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index d11175dc5b6..3f4743f1e01 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1624,6 +1624,14 @@  void cdns3_ep_config(struct cdns3_endpoint *priv_ep)
 	else
 		priv_ep->trb_burst_size = 16;
 
+	/*
+	 * The Endpoint is configured to handle a maximum packet size of
+	 * max_packet_size. Hence, set priv_ep->endpoint.maxpacket to
+	 * max_packet_size. This is necessary to ensure that the TD_SIZE
+	 * is calculated correctly in cdns3_ep_run_transfer().
+	 */
+	priv_ep->endpoint.maxpacket = max_packet_size;
+
 	ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
 					     !!priv_ep->dir);
 	if (ret) {

Regards

Gokul