SK-AM62P-LP: How to configure the MIPI DSI clock bandwidth ?

Hello,

Just to confirm, you were asking about MIPI DSI for display, right?

Thanks,

Jianzhong

Hi, 

Yes, is MIPI dsi, we plan to use lower clock on 4 lanes mipi panel and higher clock on 2 lanes panel. Wish to understand how to change the mipi clock.

Thanks.

Hi,
Lane speed is calculated as (h_tot * v_tot * fps * 24 / num_lanes)
Here h_tot and v_tot are dependent on your display resolution, num_lanes is the number of MIPI lanes your display supports.
Only way to increase lane speed is to increase your fps.
You can do this by configuring clock in display timing parameters accordingly.

Sorry for late reply, I fail to comprehend how to "configure clock in display timing" are you able to point me to some kernel codes in the SDK or any description in the am62p TRM ?

Thanks.

Hi,
You may take this example: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/gpu/drm/panel/panel-simple.c?h=ti-linux-6.12.y#n3859 
Here the clock has been calculated and set as per 60fps.