PROCESSOR-SDK-AM437X: U-Boot 2024 SPL not booting on AM4378 Board

Thanks for your detailed issue description.
The latest AM437x Linux SDK is 9.3.5.2 (u-boot 2023.04)
https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM437X/09.03.05.02
Have you tried Linux SDK 9.3.5.2?
Best,
-Hong

@Hong Yes, i did try the same steps for u-boot 2023.04.

But No result.

I'm attaching the working boot log with AM437x Linux SDK 9.3.5.2 on TI AM437x EVM.
It will be useful to use JTAG to debug the issue. Do we have JTAG access on your board?
Best,
-Hong

U-Boot SPL 2023.04 (Jun 24 2025 - 16:22:14 -0500)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!


U-Boot 2023.04 (Jun 24 2025 - 16:22:14 -0500)

CPU  : AM437X-GP rev 1.2
Model: TI AM437x GP EVM
DRAM:  2 GiB
Core:  36 devices, 18 uclasses, devicetree: separate
PMIC:  TPS65218
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... 
Net:   eth2: ethernet@4a100000
Hit any key to stop autoboot:  2  0 
=> md.l 0x44e10040 1
44e10040: 00400301                             ..@.
=> ls mmc 0
   123547   am437x-gp-evm.dtb
   112421   am437x-idk-evm.dtb
   118979   am437x-sk-evm.dtb
   122333   am43x-epos-evm.dtb
            extlinux/
   158843   MLO
   814164   u-boot.img
      717   uEnv.txt
  7700992   zImage
     2415   bmaptool_note.txt
            System Volume Information/
            am4_9.3.5.2_prebuilt/

9 file(s), 3 dir(s)

=> ls mmc 0 extlinux
            ./
            ../
      177   extlinux.conf

1 file(s), 2 dir(s)

=> boot
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1:	Arago
Retrieving file: /extlinux/../zImage
append: root=PARTUUID=39139979-02 rootwait rw console=ttyO0,115200n8,115200
Retrieving file: /extlinux/../am437x-gp-evm.dtb
This will not be a case any time
This will not be a case any time
Kernel image @ 0x82000000 [ 0x000000 - 0x758200 ]
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
Working FDT set to 88000000
   Loading Device Tree to 8ffde000, end 8ffff29a ... OK
Working FDT set to 8ffde000

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 6.1.119 (jason@laptop) (arm-none-linux-gnueabihf-gcc (Arm GNU Toolchain 11.3.Rel1) 11.3.1 20220712, GNU ld (Arm GNU Toolchain 11.3.Rel1) 2.38.20220708) #1 PREEMPT Tue Jun 24 16:30:33 CDT 2025
[    0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: TI AM437x GP EVM
[    0.000000] Memory policy: Data cache writeback
[    0.000000] efi: UEFI not found.
[    0.000000] cma: Reserved 64 MiB at 0xfb800000
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000080000000-0x00000000afffffff]
[    0.000000]   HighMem  [mem 0x00000000b0000000-0x00000000ffffefff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x00000000ffffefff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000ffffefff]
[    0.000000] CPU: All CPU(s) started in SVC mode.
[    0.000000] AM437x ES1.2 (sgx neon)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 522751
[    0.000000] Kernel command line: root=PARTUUID=39139979-02 rootwait rw console=ttyO0,115200n8,115200
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 1995844K/2097148K available (11264K kernel code, 1479K rwdata, 3232K rodata, 1024K init, 285K bss, 35768K reserved, 65536K cma-reserved, 1245180K highmem)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] trace event string verifier disabled
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu: 	RCU event tracing is enabled.
[    0.000000] 	Trampoline variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] L2C: platform modifies aux control register: 0x0e030000 -> 0x3e430000
[    0.000000] L2C: DT/platform modifies aux control register: 0x0e030000 -> 0x3e430000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] OMAP L2C310: ROM does not support power control setting
[    0.000000] L2C-310 dynamic clock gating disabled, standby mode disabled
[    0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c9, AUX_CTRL 0x4e430000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] TI gptimer clocksource: always-on /ocp@44000000/interconnect@44c00000/segment@200000/target-module@31000
[    0.000001] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[    0.000019] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[    0.000149] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000157] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000450] TI gptimer clockevent: 24000000 Hz at /ocp@44000000/interconnect@48000000/segment@0/target-module@40000
[    0.002048] Console: colour dummy device 80x30
[    0.002084] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
[    0.002090] This ensures that you still see kernel messages. Please
[    0.002094] update your kernel commandline.
[    0.002125] Calibrating delay loop... 1987.37 BogoMIPS (lpj=9936896)
[    0.057636] CPU: Testing write buffer coherency: ok
[    0.057705] CPU0: Spectre v2: using BPIALL workaround
[    0.057716] pid_max: default: 32768 minimum: 301
[    0.057908] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
[    0.057936] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
[    0.059683] cblist_init_generic: Setting adjustable number of callback queues.
[    0.059698] cblist_init_generic: Setting shift to 0 and lim to 1.
[    0.059853] Setting up static identity map for 0x80100000 - 0x80100060
[    0.060003] rcu: Hierarchical SRCU implementation.
[    0.060009] rcu: 	Max phase no-delay instances is 1000.
[    0.062153] EFI services will not be available.
[    0.062800] devtmpfs: initialized
[    0.077609] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.077925] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.077950] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[    0.082910] pinctrl core: initialized pinctrl subsystem
[    0.083941] DMI not present or invalid.
[    0.084593] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.086787] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.087875] thermal_sys: Registered thermal governor 'step_wise'
[    0.087974] cpuidle: using governor menu
[    0.107237] platform display: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@300000/target-module@2a000/dss@0
[    0.108053] No ATAGs?
[    0.108074] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.108083] hw-breakpoint: maximum watchpoint size is 4 bytes.
[    0.130085] iommu: Default domain type: Translated 
[    0.130101] iommu: DMA domain TLB invalidation policy: strict mode 
[    0.131848] SCSI subsystem initialized
[    0.138184] usbcore: registered new interface driver usbfs
[    0.138227] usbcore: registered new interface driver hub
[    0.138267] usbcore: registered new device driver usb
[    0.138703] pps_core: LinuxPPS API ver. 1 registered
[    0.138711] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.138730] PTP clock support registered
[    0.138885] EDAC MC: Ver: 3.0.0
[    0.141208] clocksource: Switched to clocksource dmtimer
[    0.162550] NET: Registered PF_INET protocol family
[    0.162977] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
[    0.164804] tcp_listen_portaddr_hash hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.164846] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.164862] TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
[    0.164924] TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.165118] TCP: Hash tables configured (established 8192 bind 8192)
[    0.165305] UDP hash table entries: 512 (order: 1, 8192 bytes, linear)
[    0.165335] UDP-Lite hash table entries: 512 (order: 1, 8192 bytes, linear)
[    0.165521] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.166072] RPC: Registered named UNIX socket transport module.
[    0.166084] RPC: Registered udp transport module.
[    0.166088] RPC: Registered tcp transport module.
[    0.166092] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.166102] PCI: CLS 0 bytes, default 64
[    0.167302] Initialise system trusted keyrings
[    0.167715] workingset: timestamp_bits=30 max_order=19 bucket_order=0
[    0.172449] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.181604] NFS: Registering the id_resolver key type
[    0.181662] Key type id_resolver registered
[    0.181669] Key type id_legacy registered
[    0.181762] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.181771] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.181811] ntfs: driver 2.1.32 [Flags: R/O].
[    0.182480] Key type asymmetric registered
[    0.182494] Asymmetric key parser 'x509' registered
[    0.182648] bounce: pool size: 64 pages
[    0.182759] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[    0.182769] io scheduler mq-deadline registered
[    0.182776] io scheduler kyber registered
[    0.274092] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
[    0.276368] STMicroelectronics ASC driver initialized
[    0.295232] brd: module loaded
[    0.305255] loop: module loaded
[    0.315357] CAN device driver interface
[    0.315749] e1000e: Intel(R) PRO/1000 Network Driver
[    0.315754] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    0.315821] igb: Intel(R) Gigabit Ethernet Network Driver
[    0.315826] igb: Copyright (c) 2007-2014 Intel Corporation.
[    0.316533] pegasus: Pegasus/Pegasus II USB Ethernet driver
[    0.316579] usbcore: registered new interface driver pegasus
[    0.316617] usbcore: registered new interface driver asix
[    0.316645] usbcore: registered new interface driver ax88179_178a
[    0.316671] usbcore: registered new interface driver cdc_ether
[    0.316713] usbcore: registered new interface driver smsc75xx
[    0.316750] usbcore: registered new interface driver smsc95xx
[    0.316784] usbcore: registered new interface driver net1080
[    0.316810] usbcore: registered new interface driver cdc_subset
[    0.316845] usbcore: registered new interface driver zaurus
[    0.316882] usbcore: registered new interface driver cdc_ncm
[    0.317546] usbcore: registered new interface driver usb-storage
[    0.321802] i2c_dev: i2c /dev entries driver
[    0.323790] cpuidle: enable-method property 'ti,am4372' found operations
[    0.324384] sdhci: Secure Digital Host Controller Interface driver
[    0.324392] sdhci: Copyright(c) Pierre Ossman
[    0.324544] Synopsys Designware Multimedia Card Interface Driver
[    0.324703] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.325138] ledtrig-cpu: registered to indicate activity on CPUs
[    0.325500] usbcore: registered new interface driver usbhid
[    0.325509] usbhid: USB HID core driver
[    0.328407] NET: Registered PF_INET6 protocol family
[    0.342373] Segment Routing with IPv6
[    0.342434] In-situ OAM (IOAM) with IPv6
[    0.342517] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    0.343204] NET: Registered PF_PACKET protocol family
[    0.343216] can: controller area network core
[    0.343302] NET: Registered PF_CAN protocol family
[    0.343310] can: raw protocol
[    0.343318] can: broadcast manager protocol
[    0.343329] can: netlink gateway - max_hops=1
[    0.343580] Key type dns_resolver registered
[    0.343740] ThumbEE CPU extension supported.
[    0.343756] Registering SWP/SWPB emulation handler
[    0.344504] omap_voltage_late_init: Voltage driver support not added
[    0.345443] Loading compiled-in X.509 certificates
[    0.419262] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/pinmux_wlan_pins_sleep
[    0.419304] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/pinmux_debugss_pins
[    0.419328] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/unused_pins
[    0.419352] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/ddr_vtt_toggle_default
[    0.419375] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/pinmux_wlan_pins_default
[    0.420203] pinctrl-single 44e10800.pinmux: 199 pins, size 796
[    0.434982] ti-sysc: probe of 44e31000.target-module failed with error -16
[    0.458222] i2c 1-0030: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@300000/target-module@26000/vpfe@0
[    0.458675] omap_i2c 4802a000.i2c: bus 1 rev0.12 at 100 kHz
[    0.473805] ti-sysc: probe of 48040000.target-module failed with error -16
[    0.478721] gpio gpiochip0: (gpio-0-31): not an immutable chip, please consider fixing it!
[    0.479044] OMAP GPIO hardware version 0.1
[    0.492584] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
[    0.502772] omap8250 481a6000.serial: No clock speed specified: using default: 48000000
[    0.503670] 481a6000.serial: ttyS3 at MMIO 0x481a6000 (irq = 57, base_baud = 3000000) is a 8250
[    0.514447] gpio gpiochip1: (gpio-32-63): not an immutable chip, please consider fixing it!
[    0.545026] omap_rng 48310000.rng: Random Number Generator ver. 20
[    0.546827] gpio gpiochip2: (gpio-64-95): not an immutable chip, please consider fixing it!
[    0.547156] random: crng init done
[    0.553173] gpio-104 (SelLCDorHDMI): hogged as output/high
[    0.553227] gpio gpiochip3: (gpio-96-127): not an immutable chip, please consider fixing it!
[    0.554775] i2c 1-0030: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@300000/target-module@26000/vpfe@0
[    0.554937] platform 48326000.vpfe: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@0/target-module@2a000/i2c@0/ov2659@30
[    0.562649] platform 48328000.vpfe: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/ov2659@30
[    0.564799] platform display: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@300000/target-module@2a000/dss@0
[    0.565010] platform 4832a000.dss: Fixed dependency cycle(s) with /display
[    0.651229] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    0.663499] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    0.664030] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
[    0.664046] cpsw-switch 4a100000.switch: ALE Table size 1024
[    0.664144] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
[    0.664157] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
[    0.664201] cpsw-switch 4a100000.switch: Detected MACID = 34:b1:f7:3d:ba:b9
[    0.665258] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010F 1.15 (0)
[    0.683053] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
[    0.683081] edma 49000000.dma: TI EDMA DMA engine driver
[    0.707608] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    0.707632] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.727388] gpio-151 (SelEMMCorNAND): hogged as output/low
[    0.727458] gpio gpiochip5: (gpio-128-159): not an immutable chip, please consider fixing it!
[    0.728454] omap8250 44e09000.serial: No clock speed specified: using default: 48000000
[    0.741974] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 70, base_baud = 3000000) is a 8250
[    2.736063] printk: console [ttyS0] enabled
[    2.773510] tps65218-pwrbutton: Failed to locate of_node [id: -2]
[    2.780020] tps65218-gpio: Failed to locate of_node [id: -2]
[    2.798952] platform 48328000.vpfe: Fixed dependency cycle(s) with /ocp@44000000/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/ov2659@30
[    2.812845] i2c 0-0030: Fixed dependency cycle(s) with /ocp@44000000/interconnect@48000000/segment@300000/target-module@28000/vpfe@0
[    2.825147] omap_i2c 44e0b000.i2c: bus 0 rev0.12 at 100 kHz
[    2.832727] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
[    2.843230] sdhci-omap 47810000.mmc: supply pbias not found, using dummy regulator
[    2.852122] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xdc
[    2.858524] nand: Micron MT29F4G08ABAEAWP
[    2.862688] sdhci-omap 47810000.mmc: supply vqmmc not found, using dummy regulator
[    2.870651] sdhci-omap 48060000.mmc: Got CD GPIO
[    2.875520] nand: 512 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224
[    2.883332] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
[    2.891815] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
[    2.900060] Using OMAP_ECC_BCH16_CODE_HW ECC scheme
[    2.905870] 10 fixed-partitions partitions found on MTD device omap2-nand.0
[    2.913908] Creating 10 MTD partitions on "omap2-nand.0":
[    2.919429] 0x000000000000-0x000000040000 : "NAND.SPL"
[    2.926197] 0x000000040000-0x000000080000 : "NAND.SPL.backup1"
[    2.933443] 0x000000080000-0x0000000c0000 : "NAND.SPL.backup2"
[    2.939381] mmc1: SDHCI controller on 47810000.mmc [47810000.mmc] using External DMA
[    2.949141] 0x0000000c0000-0x000000100000 : "NAND.SPL.backup3"
[    2.955231] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
[    2.965090] 0x000000100000-0x000000180000 : "NAND.u-boot-spl-os"
[    2.973102] 0x000000180000-0x000000280000 : "NAND.u-boot"
[    2.980762] 0x000000280000-0x0000002c0000 : "NAND.u-boot-env"
[    2.988281] 0x0000002c0000-0x000000300000 : "NAND.u-boot-env.backup1"
[    2.996184] 0x000000300000-0x000000a00000 : "NAND.kernel"
[    3.004255] 0x000000a00000-0x000020000000 : "NAND.file-system"
[    3.051015] mmc0: new high speed SDHC card at address aaaa
[    3.062661] mmcblk0: mmc0:aaaa SC16G 14.8 GiB 
[    3.078402]  mmcblk0: p1 p2
[    3.103677] clk: Disabling unused clocks
[    3.192381] EXT4-fs (mmcblk0p2): recovery complete
[    3.200584] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Quota mode: disabled.
[    3.209640] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    3.220130] devtmpfs: mounted
[    3.225004] Freeing unused kernel image (initmem) memory: 1024K
[    3.231182] Run /sbin/init as init process
[    3.637939] systemd[1]: System time before build time, advancing clock.
[    3.680396] systemd[1]: systemd 250.5+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid)
[    3.713297] systemd[1]: Detected architecture arm.

Welcome to Arago 2023.10!

[    3.765279] systemd[1]: Hostname set to <am437x-evm>.
[    4.063528] systemd-sysv-generator[80]: SysV service '/etc/init.d/thermal-zone-init' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    4.574571] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.685011] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.821357] systemd[1]: Queued start job for default target Graphical Interface.
[    4.834022] systemd[1]: Created slice Slice /system/getty.
[  OK  ] Created slice Slice /system/getty.
[    4.876768] systemd[1]: Created slice Slice /system/modprobe.
[  OK  ] Created slice Slice /system/modprobe.
[    4.914118] systemd[1]: Created slice Slice /system/serial-getty.
[  OK  ] Created slice Slice /system/serial-getty.
[    4.952613] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    4.992643] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password �ts to Console Directory Watch.
[    5.032068] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password R�uests to Wall Directory Watch.
[    5.073523] systemd[1]: Reached target Path Units.
[  OK  ] Reached target Path Units.
[    5.112188] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    5.151757] systemd[1]: Reached target Slice Units.
[  OK  ] Reached target Slice Units.
[    5.192349] systemd[1]: Reached target Swaps.
[  OK  ] Reached target Swaps.
[    5.247901] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    5.292143] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    5.356742] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    5.392219] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    5.453539] systemd[1]: Journal Audit Socket was skipped because of a failed condition check (ConditionSecurity=audit).
[    5.466832] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    5.502696] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    5.544403] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    5.584129] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    5.622523] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    5.663579] systemd[1]: Listening on User Database Manager Socket.
[  OK  ] Listening on User Database Manager Socket.
[    5.702851] systemd[1]: Huge Pages File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
[    5.752050] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.796090] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.872535] systemd[1]: Mounting Kernel Trace File System...
         Mounting Kernel Trace File System...
[    5.900264] systemd[1]: Mounting Temporary Directory /tmp...
         Mounting Temporary Directory /tmp...
[    5.942760] systemd[1]: Create List of Static Device Nodes was skipped because of a failed condition check (ConditionFileNotEmpty=/lib/modules/6.1.119/modules.devname).
[    5.992481] systemd[1]: Starting Load Kernel Module configfs...
         Starting Load Kernel Module configfs...
[    6.017465] systemd[1]: Starting Load Kernel Module drm...
         Starting Load Kernel Module drm...
[    6.092721] systemd[1]: Starting Load Kernel Module fuse...
         Starting Load Kernel Module fuse...
[    6.128297] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    6.192628] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    6.202932] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/).
[    6.219531] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
[    6.234379] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
[    6.281936] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    6.314188] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    6.354548] systemd[1]: Starting Generate network units from Kernel command line...
         Starting Generate network �ts from Kernel command line...
[    6.442709] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems...
[    6.502622] systemd[1]: Starting Coldplug All udev Devices...
         Starting Coldplug All udev Devices...
[    6.583446] EXT4-fs (mmcblk0p2): re-mounted. Quota mode: disabled.
[    6.606603] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    6.632606] systemd[1]: Mounted POSIX Message Queue File System.
[  OK  ] Mounted POSIX Message Queue File System.
[    6.662394] systemd[1]: Mounted Kernel Debug File System.
[  OK  ] Mounted Kernel Debug File System.
[    6.702366] systemd[1]: Mounted Kernel Trace File System.
[  OK  ] Mounted Kernel Trace File System.
[    6.722533] systemd[1]: Mounted Temporary Directory /tmp.
[  OK  ] Mounted Temporary Directory /tmp.
[    6.743292] systemd[1]: modprobe@configfs.service: Deactivated successfully.
[    6.771568] systemd[1]: Finished Load Kernel Module configfs.
[  OK  ] Finished Load Kernel Module configfs.
[    6.793602] systemd[1]: modprobe@drm.service: Deactivated successfully.
[    6.821736] systemd[1]: Finished Load Kernel Module drm.
[  OK  ] Finished Load Kernel Module drm.
[    6.838676] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Finished Load Kernel Module fuse.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star�progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[  OK  ] Finished Generate network units from Kernel command line.
[  OK  ] Finished Remount Root and Kernel File Systems.
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[    7.380990] systemd-journald[91]: Received client request to flush runtime journal.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Finished Flush Journal to Persistent Storage.
[  OK  ] Finished Apply Kernel Variables.
[  OK  ] Finished Create Static Device Nodes in /dev.
[  OK  ] Reached target Preparation for Local File Systems.
         Mounting /media/ram...
         Mounting /var/volatile...
         Starting Rule-based Manage�for Device Events and Files...
[  OK  ] Mounted /media/ram.
[  OK  ] Mounted /var/volatile.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Finished Load/Save Random Seed.
[  OK  ] Finished Create Volatile Files and Directories.
         Starting Network Time Synchronization...
         Starting Record System Boot/Shutdown in UTMP...
[  OK  ] Started Rule-based Manager for Device Events and Files.
[  OK  ] Finished Record System Boot/Shutdown in UTMP.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Set.
[  OK  ] Finished Coldplug All udev Devices.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timer Units.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API...
[  OK  ] Listening on dropbear.socket.
[  OK  ] Listening on PC/SC Smart Card Daemon Activation Socket.
         Starting Weston socket...
         Starting D-Bus System Message Bus...
         Starting Reboot and dump vmcore via kexec...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Listening on Weston socket.
[  OK  ] Found device /dev/ttyS0.
[  OK  ] Finished Reboot and dump vmcore via kexec.
[  OK  ] Reached target Socket Units.
[  OK  ] Started D-Bus System Message Bus.
[  OK  ] Reached target Basic System.
[  OK  ] Started Job spooling tools.
[  OK  ] Started Periodic Command Scheduler.
         Starting DEMO...
         Starting Print notice about GPLv3 packages...
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
         Starting Lighttpd Daemon...
         Starting Telephony service...
         Starting Expand the rootfs�ll size of the boot device....
[  OK  ] Started strongSwan IPsec I�IKEv2 daemon using ipsec.conf.
[   12.563557] mtdblock: MTD device 'NAND.SPL.backup1' is NAND, please consider using UBI block devices instead.
[   12.576354] mtdblock: MTD device 'NAND.SPL.backup2' is NAND, please consider using UBI block devices instead.
[   12.609755] mtdblock: MTD device 'NAND.SPL' is NAND, please consider using UBI block devices instead.
[   12.619983] mtdblock: MTD device 'NAND.SPL.backup3' is NAND, please consider using UBI block devices instead.
[   12.647278] mtdblock: MTD device 'NAND.u-boot-spl-os' is NAND, please consider using UBI block devices instead.
         Starting User Login Management...
[   12.679970] mtdblock: MTD device 'NAND.u-boot' is NAND, please consider using UBI block devices instead.
         Starting Telnet Server...
[  OK  ] Finished IPv6 Packet Filtering Framework.
[  OK  ] Finished IPv4 Packet Filtering Framework.
[   13.303220] pwm-backlight backlight: supply power not found, using dummy regulator
[   13.329175] mtdblock: MTD device 'NAND.u-boot-env' is NAND, please consider using UBI block devices instead.
[   13.376158] mtdblock: MTD device 'NAND.u-boot-env.backup1' is NAND, please consider using UBI block devices instead.
[  OK  ] Started Lighttpd Daemon.
[  OK  ] Started DEMO.
[   13.497107] platform backlight: deferred probe pending
[  OK  ] Finished Telnet Server.
[   13.571037] platform display: deferred probe pending
[   13.665170] mtdblock: MTD device 'NAND.kernel' is NAND, please consider using UBI block devices instead.
[   13.951554] mtdblock: MTD device 'NAND.file-system' is NAND, please consider using UBI block devices instead.
[  OK  ] Finished Expand the rootfs�full size of the boot device..
[   16.498187] mtdblock: MTD device 'NAND.u-boot-spl-os' is NAND, please consider using UBI block devices instead.
[   17.115376] mtdblock: MTD device 'NAND.SPL.backup2' is NAND, please consider using UBI block devices instead.
[   17.796995] mtdblock: MTD device 'NAND.SPL' is NAND, please consider using UBI block devices instead.
[  OK  ] Started Telephony service.
[   18.279864] mtdblock: MTD device 'NAND.file-system' is NAND, please consider using UBI block devices instead.
[   18.908949] mtdblock: MTD device 'NAND.u-boot-env.backup1' is NAND, please consider using UBI block devices instead.
[   19.296255] mtdblock: MTD device 'NAND.u-boot' is NAND, please consider using UBI block devices instead.
[   19.607234] mtdblock: MTD device 'NAND.SPL.backup3' is NAND, please consider using UBI block devices instead.
[   19.739934] mtdblock: MTD device 'NAND.SPL.backup1' is NAND, please consider using UBI block devices instead.
[   20.167609] mtdblock: MTD device 'NAND.kernel' is NAND, please consider using UBI block devices instead.
[   20.760090] mtdblock: MTD device 'NAND.u-boot-env' is NAND, please consider using UBI block devices instead.
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPL-3.0 packages:
	adwaita-icon-theme-symbolic
	autoconf
	bash-dev
	bash
	bc
	binutils
	cifs-utils
	coreutils-stdbuf
	coreutils
	cpio
	cpp-symlinks
	cpp
	dosfstools
	elfutils
	g++-symlinks
	g++
	gawk
	gcc-symlinks
	gcc
	gdb
	gdbserver
	gettext
	glmark2
	gnu-config
	gzip
	hidapi
	less
	libasm1
	libatomic-dev
	libatomic1
	libbfd
	libdebuginfod1
	libdw1
	libelf1
	libgcc-s-dev
	libgcc1
	libgdbm-compat4
	libgdbm-dev
	libgdbm6
	libgettextlib
	libgettextsrc
	libgmp10
	libidn2-0
	libmpc3
	libmpfr6
	libopcodes
	libqt5charts-examples
	libqt5charts-plugins
	libqt5charts-qmlplugins
	libqt5charts5
	libqt5sensors-plugins
	libqt5sensors-qmlplugins
	libqt5sensors5
	libqt5serialport-examples
	libqt5serialport-plugins
	libqt5serialport-qmlplugins
	libqt5serialport5
	libqt5svg-examples
	libqt5svg-plugins
	libqt5svg-qmlplugins
	libqt5svg5
	libqt5virtualkeyboard-plugins
	libqt5virtualkeyboard-qmlplugins
	libqt5virtualkeyboard5
	libqt5webchannel-plugins
	libqt5webchannel-qmlplugins
	libqt5webchannel5
	libreadline-dev
	libreadline8
	libstdc++-dev
	libstdc++6
	libunistring2
	m4-dev
	m4
	make
	nettle
	parted
	pdm-anomaly-detection
	piglit
	qt3d-plugins
	qt3d-qmlplugins
	qt3d
	qtbase-examples
	qtbase-plugins
	qtbase-qmlplugins
	qtbase
	qtconnectivity-plugins
	qtconnectivity-qmlplugins
	qtconnectivity
	qtdeclarative-plugins
	qtdeclarative-qmlplugins
	qtdeclarative-tools
	qtdeclarative
	qtgraphicaleffects-qmlplugins
	qtlocation-examples
	qtlocation-plugins
	qtlocation-qmlplugins
	qtlocation
	qtmultimedia-examples
	qtmultimedia-plugins
	qtmultimedia-qmlplugins
	qtmultimedia
	qtquics-qmlplugins.control
	qtquics2-plugins.control
	qtquics2-qmlplugins.control
	qtquics2.control
	qtscript-examples
	qtscript-plugins
	qtscript-qmlplugins
	qtscript
	qtwayland-examples
	qtwayland-plugins
	qtwayland-qmlplugins
	qtwayland
	tar
	which

If you do not wish to distribute GPL-3.0 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************
[  OK  ] Started User Login Management.
[  OK  ] Finished Print notice about GPLv3 packages.
[  OK  ] Created slice Slice /system/systemd-fsck.
[  OK  ] Reached target Preparation for Network.
[  OK  ] Listening on Load/Save RF �itch Status /dev/rfkill Watch.
         Starting File System Check on /dev/mmcblk0p1...
         Starting Network Configuration...
[  OK  ] Started Network Configuration.
         Starting Network Name Resolution...
[   28.494791] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
[   28.641326] Micrel KSZ9031 Gigabit PHY 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Network.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
         Starting Enable and configure wl18xx bluetooth stack...
         Starting containerd container runtime...
[  OK  ] Started Netperf Benchmark Server.
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting Simple Network Ma�ent Protocol (SNMP) Daemon....
         Starting Permit User Sessions...
[  OK  ] Finished Permit User Sessions.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS0.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
         Starting Weston, a Wayland�ositor, as a system service...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
         Starting User Database Manager...
[  OK  ] Finished Enable and configure wl18xx bluetooth stack.
[  OK  ] Started Simple Network Man�ement Protocol (SNMP) Daemon..
[  OK  ] Started User Database Manager.
[  OK  ] Created slice User Slice of UID 1000.
         Starting User Runtime Directory /run/user/1000...
[  OK  ] Finished User Runtime Directory /run/user/1000.
         Starting User Manager for UID 1000...
[  OK  ] Finished File System Check on /dev/mmcblk0p1.
         Mounting /run/media/boot-mmcblk0p1...
[   33.072099] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[  OK  ] Mounted /run/media/boot-mmcblk0p1.
[  OK  ] Started containerd container runtime.


 _____                    _____           _         _   
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_ 
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|  
              |___|                    |___|            

Arago Project am437x-evm -

Arago 2023.10 am437x-evm -

am437x-evm login: root

root@am437x-evm:~# uname -a
Linux am437x-evm 6.1.119 #1 PREEMPT Tue Jun 24 16:30:33 CDT 2025 armv7l armv7l armv7l GNU/Linux
root@am437x-evm:~# 

Yes @hong 

Thanks for sharing the logs — however, they appear to be from the EVM.

My board is a production unit based on the AM4378 and is already in the market, running reliably with U-Boot 2021.

I have ported the same modifications from U-Boot 2021 to U-Boot 2024. Interestingly, the u-boot.img from the 2024 build works fine when used with the old (2021) MLO, which suggests the issue lies in the SPL/MLO stage of the new version.

Regarding JTAG access — the board is fully enclosed, and it's not feasible at the moment to open it and connect JTAG.

Could you please help by outlining the minimal set of changes required to get the 2024 MLO running and at least printing the SPL banner line? That would help confirm basic bring-up.

Yes, I captured the working boot log on TI reference board.
I'd recommend refer to the u-boot porting guide
https://software-dl.ti.com/processor-sdk-linux/esd/AM437X/09_03_05_02/exports/docs/linux/How_to_Guides/Board_Port/U-Boot.html

also having JTAG on board is helpful to debug the SPL non-booting issue.
Best,
-Hong

@Hong

From adc10dc5b28654be1ee0bbb8165a3d537e62c216 Mon Sep 17 00:00:00 2001
From: Kuldip Kanzariya <kuldip.kanzariya@acldigital.com>
Date: Thu, 3 Jul 2025 10:46:55 +0530
Subject: [PATCH] CUST_BOARD_PATCH

---
 arch/arm/dts/Makefile                   |   3 +-
 arch/arm/dts/am437x-myboard-u-boot.dtsi |  60 ++
 arch/arm/dts/am437x-myboard.dts         | 798 ++++++++++++++++++++++++
 arch/arm/mach-omap2/Kconfig             |   1 +
 arch/arm/mach-omap2/am33xx/Kconfig      |  29 +
 board/mycompany/myboard/Kconfig         |  17 +
 board/mycompany/myboard/MAINTAINERS     |  10 +
 board/mycompany/myboard/Makefile        |  11 +
 board/mycompany/myboard/board.c         | 796 +++++++++++++++++++++++
 board/mycompany/myboard/board.h         |  62 ++
 board/mycompany/myboard/mux.c           | 132 ++++
 common/spl/spl.c                        |   3 +
 configs/am43xx_myboard_defconfig        | 109 ++++
 generated_defconfig                     | 113 ++++
 include/configs/am43xx_myboard.h        | 160 +++++
 15 files changed, 2303 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/am437x-myboard-u-boot.dtsi
 create mode 100644 arch/arm/dts/am437x-myboard.dts
 create mode 100644 board/mycompany/myboard/Kconfig
 create mode 100644 board/mycompany/myboard/MAINTAINERS
 create mode 100644 board/mycompany/myboard/Makefile
 create mode 100644 board/mycompany/myboard/board.c
 create mode 100644 board/mycompany/myboard/board.h
 create mode 100644 board/mycompany/myboard/mux.c
 create mode 100644 configs/am43xx_myboard_defconfig
 create mode 100644 generated_defconfig
 create mode 100644 include/configs/am43xx_myboard.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4d03a0f5b30..b0829c609b2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -542,7 +542,8 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb \
 	am4372-generic.dtb \
-	am437x-cm-t43.dtb
+	am437x-cm-t43.dtb \
+	am437x-myboard.dtb
 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
 dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
 
diff --git a/arch/arm/dts/am437x-myboard-u-boot.dtsi b/arch/arm/dts/am437x-myboard-u-boot.dtsi
new file mode 100644
index 00000000000..6393170ad22
--- /dev/null
+++ b/arch/arm/dts/am437x-myboard-u-boot.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "dra7.dtsi"
+ */
+
+#include "am4372-u-boot.dtsi"
+
+/{
+	ocp {
+		bootph-pre-ram;
+	};
+};
+
+&uart0 {
+	bootph-pre-ram;
+};
+
+&mmc1 {
+	bootph-pre-ram;
+};
+
+&mac {
+	bootph-pre-ram;
+};
+
+&davinci_mdio {
+	bootph-pre-ram;
+};
+
+&cpsw_emac0 {
+	bootph-pre-ram;
+};
+
+&phy_sel {
+	bootph-pre-ram;
+};
+
+&i2c0 {
+	bootph-pre-ram;
+};
+
+&l4_wkup {
+	bootph-pre-ram;
+};
+
+&scm {
+	bootph-pre-ram;
+};
+
+&scm_conf {
+	bootph-pre-ram;
+};
+
+&ethphy0 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/am437x-myboard.dts b/arch/arm/dts/am437x-myboard.dts
new file mode 100644
index 00000000000..b9a09e62db3
--- /dev/null
+++ b/arch/arm/dts/am437x-myboard.dts
@@ -0,0 +1,798 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/* AM437x GP EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "TI AM437x MY BOARD";
+	compatible = "ti,am437x-myboard","ti,am4372","ti,am43";
+
+	aliases {
+		display0 = &lcd0;
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	vmmcsd_fixed: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcsd_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	vtt_fixed: fixedregulator-vtt {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt_fixed";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	vmmcwl_fixed: fixedregulator-mmcwl {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcwl_fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 51 53 56 62 75 101 152 255>;
+		default-brightness-level = <8>;
+	};
+
+	matrix_keypad: matrix_keypad@0 {
+		compatible = "gpio-matrix-keypad";
+		debounce-delay-ms = <5>;
+		col-scan-delay-us = <2>;
+
+		row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+				&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+				&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
+
+		col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+				&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
+
+		linux,keymap = <0x00000201      /* P1 */
+				0x00010202      /* P2 */
+				0x01000067      /* UP */
+				0x0101006a      /* RIGHT */
+				0x02000069      /* LEFT */
+				0x0201006c>;      /* DOWN */
+		};
+
+	lcd0: display {
+		compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+		label = "lcd";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_pins>;
+
+		/*
+		 * SelLCDorHDMI, LOW to select HDMI. This is not really the
+		 * panel's enable GPIO, but we don't have HDMI driver support nor
+		 * support to switch between two displays, so using this gpio as
+		 * panel's enable should be safe.
+		 */
+		enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+
+		panel-timing {
+			clock-frequency = <33000000>;
+			hactive = <800>;
+			vactive = <480>;
+			hfront-porch = <210>;
+			hback-porch = <16>;
+			hsync-len = <30>;
+			vback-porch = <10>;
+			vfront-porch = <22>;
+			vsync-len = <13>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <1>;
+		};
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+
+	/* fixed 12MHz oscillator */
+	refclk: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+};
+
+&am43xx_pinmux {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&wlan_pins_default>;
+	pinctrl-1 = <&wlan_pins_sleep>;
+
+	i2c0_pins: i2c0_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+			AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c1_pins: i2c1_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+			AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	ecap0_pins: backlight_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+		>;
+	};
+
+	pixcir_ts_pins: pixcir_ts_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_txen */
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rxctl */
+			AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd3 */
+			AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd2 */
+			AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd1 */
+			AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd0 */
+			AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd3 */
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd2 */
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd1 */
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	nand_flash_x8: nand_flash_x8 {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+			AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+			AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+
+	dss_pins: dss_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+			AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+			AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+			AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+			AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+			AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+			AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+			AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+
+		>;
+	};
+
+	lcd_pins: lcd_pins {
+		pinctrl-single,pins = <
+			/* GPIO 5_8 to select LCD / HDMI */
+			AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
+		>;
+	};
+
+	dcan0_default: dcan0_default_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
+			AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
+		>;
+	};
+
+	dcan1_default: dcan1_default_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)		/* uart1_rxd.d_can1_tx */
+			AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_txd.d_can1_rx */
+		>;
+	};
+
+	vpfe0_pins_default: vpfe0_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+			AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+			AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+			AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+			AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+			AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+			AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+			AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+			AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+			AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+			AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+			AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+			AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+		>;
+	};
+
+	vpfe0_pins_sleep: vpfe0_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
+			AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
+			AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
+			AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
+			AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
+			AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
+			AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
+			AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
+			AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
+			AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
+			AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
+			AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
+			AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
+		>;
+	};
+
+	vpfe1_pins_default: vpfe1_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
+			AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
+			AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
+			AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
+			AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
+			AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
+			AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
+			AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
+			AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
+			AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
+			AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
+			AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
+			AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
+		>;
+	};
+
+	vpfe1_pins_sleep: vpfe1_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
+			AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
+			AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
+			AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
+			AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
+			AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
+			AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
+			AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
+			AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
+			AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
+			AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
+			AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
+			AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
+		>;
+	};
+
+	mmc3_pins_default: pinmux_mmc3_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
+			AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
+			AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
+			AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
+			AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
+		>;
+	};
+
+	mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_clk.mmc2_clk */
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_csn3.mmc2_cmd */
+			AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a1.mmc2_dat0 */
+			AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a2.mmc2_dat1 */
+			AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a3.mmc2_dat2 */
+			AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_be1n.mmc2_dat3 */
+		>;
+	};
+
+	wlan_pins_default: pinmux_wlan_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
+			AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
+			AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
+		>;
+	};
+
+	wlan_pins_sleep: pinmux_wlan_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
+			AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
+			AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
+		>;
+	};
+
+	uart3_pins: uart3_pins {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)		/* uart3_rxd.uart3_rxd */
+			AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
+			AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_ctsn.uart3_ctsn */
+			AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
+		>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <100000>;
+
+	tps65218: tps65218@24 {
+		reg = <0x24>;
+		compatible = "ti,tps65218";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		dcdc1: regulator-dcdc1 {
+			compatible = "ti,tps65218-dcdc1";
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc2: regulator-dcdc2 {
+			compatible = "ti,tps65218-dcdc2";
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3: regulator-dcdc3 {
+			compatible = "ti,tps65218-dcdc3";
+			regulator-name = "vdcdc3";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+		dcdc5: regulator-dcdc5 {
+			compatible = "ti,tps65218-dcdc5";
+			regulator-name = "v1_0bat";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+
+		dcdc6: regulator-dcdc6 {
+			compatible = "ti,tps65218-dcdc6";
+			regulator-name = "v1_8bat";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		ldo1: regulator-ldo1 {
+			compatible = "ti,tps65218-ldo1";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+
+	ov2659@30 {
+		compatible = "ovti,ov2659";
+		reg = <0x30>;
+
+		clocks = <&refclk 0>;
+		clock-names = "xvclk";
+
+		port {
+			ov2659_0: endpoint {
+				remote-endpoint = <&vpfe1_ep>;
+				link-frequencies = /bits/ 64 <70000000>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	pixcir_ts@5c {
+		compatible = "pixcir,pixcir_tangoc";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pixcir_ts_pins>;
+		reg = <0x5c>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <22 0>;
+
+		attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+
+		touchscreen-size-x = <1024>;
+		touchscreen-size-y = <600>;
+	};
+
+	ov2659@30 {
+		compatible = "ovti,ov2659";
+		reg = <0x30>;
+
+		clocks = <&refclk 0>;
+		clock-names = "xvclk";
+
+		port {
+			ov2659_1: endpoint {
+				remote-endpoint = <&vpfe0_ep>;
+				link-frequencies = /bits/ 64 <70000000>;
+			};
+		};
+	};
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&tscadc {
+	status = "okay";
+
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&ecap0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ecap0_pins>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+	ti,no-reset-on-init;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mmc3 {
+	/* disable MMC3 as SDIO is not supported in U-Boot */
+	status = "disabled";
+	/* these are on the crossbar and are outlined in the
+	   xbar-event-map element */
+	dmas = <&edma 30
+		&edma 31>;
+	dma-names = "tx", "rx";
+	vmmc-supply = <&vmmcwl_fixed>;
+	bus-width = <4>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mmc3_pins_default>;
+	pinctrl-1 = <&mmc3_pins_sleep>;
+	cap-power-off-card;
+	keep-power-in-suspend;
+	ti,non-removable;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@0 {
+		compatible = "ti,wl1835";
+		reg = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&edma {
+	ti,edma-xbar-event-map = /bits/ 16 <1 30
+					    2 31>;
+};
+
+&uart3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_phy2 {
+	status = "okay";
+};
+
+&usb2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&mac {
+	slaves = <1>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&cpsw_emac0 {
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii";
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x8>;
+	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
+	nand@0,0 {
+		reg = <0 0 4>;		/* device IO registers */
+		ti,nand-ecc-opt = "bch16";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>;
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <25>;
+		gpmc,adv-wr-off-ns = <25>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <20>;
+		gpmc,oe-on-ns = <3>;
+		gpmc,oe-off-ns = <30>;
+		gpmc,access-ns = <30>;
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,wait-pin = <0>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x000c0000 0x00040000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00100000 0x00080000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x00180000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x00280000 0x00040000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x002c0000 0x00040000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00300000 0x00700000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x1f600000>;
+		};
+	};
+};
+
+&dss {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&dss_pins>;
+
+	port {
+		dpi_out: endpoint@0 {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <24>;
+		};
+	};
+};
+
+&dcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan0_default>;
+	status = "okay";
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_default>;
+	status = "okay";
+};
+
+&vpfe0 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&vpfe0_pins_default>;
+	pinctrl-1 = <&vpfe0_pins_sleep>;
+
+	port {
+		vpfe0_ep: endpoint {
+			remote-endpoint = <&ov2659_1>;
+			ti,am437x-vpfe-interface = <0>;
+			bus-width = <8>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+		};
+	};
+};
+
+&vpfe1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&vpfe1_pins_default>;
+	pinctrl-1 = <&vpfe1_pins_sleep>;
+
+	port {
+		vpfe1_ep: endpoint {
+			remote-endpoint = <&ov2659_0>;
+			ti,am437x-vpfe-interface = <0>;
+			bus-width = <8>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+		};
+	};
+};
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8465b5426d8..adcae539bb8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -197,5 +197,6 @@ source "board/ti/am43xx/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
 source "board/phytec/phycore_am335x_r2/Kconfig"
+source "board/mycompany/myboard/Kconfig"
 
 endif
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 46abf070f9d..ed3ebe62ec2 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -227,6 +227,35 @@ config TARGET_AM43XX_EVM
 	  to write software and develop hardware around
 	  an AM43xx processor subsystem.
 
+config TARGET_AM43XX_MYBOARD
+        bool "Support am43xx_myboard"
+        select BOARD_LATE_INIT
+        imply DM_I2C
+        imply DM_SPI
+        imply DM_SPI_FLASH
+        imply MTD
+        imply SPL_ENV_SUPPORT
+        imply SPL_FS_EXT4
+        imply SPL_FS_FAT
+        imply SPL_GPIO
+        imply SPL_I2C
+        imply SPL_LIBCOMMON_SUPPORT
+        imply SPL_LIBDISK_SUPPORT
+        imply SPL_LIBGENERIC_SUPPORT
+        imply SPL_MMC
+        imply SPL_NAND_SUPPORT
+        imply SPL_POWER
+        imply SPL_SERIAL
+        imply SPL_WATCHDOG
+        imply SPL_YMODEM_SUPPORT
+        help
+          This option specifies support for the AM43xx
+          GP and HS EVM development platforms.The AM437x
+          GP EVM is a standalone test, development, and
+          evaluation module system that enables developers
+          to write software and develop hardware around
+          an AM43xx processor subsystem.
+
 config TARGET_CM_T43
 	bool "Support cm_t43"
 
diff --git a/board/mycompany/myboard/Kconfig b/board/mycompany/myboard/Kconfig
new file mode 100644
index 00000000000..bbf2ce18752
--- /dev/null
+++ b/board/mycompany/myboard/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_AM43XX_MYBOARD
+
+config SYS_BOARD
+	default "myboard"
+
+config SYS_VENDOR
+	default "mycompany"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am43xx_myboard"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/mycompany/myboard/MAINTAINERS b/board/mycompany/myboard/MAINTAINERS
new file mode 100644
index 00000000000..5478dd71045
--- /dev/null
+++ b/board/mycompany/myboard/MAINTAINERS
@@ -0,0 +1,10 @@
+AM43XX BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/am43xx/
+F:	include/configs/am43xx_evm.h
+F:	configs/am43xx_evm_defconfig
+F:	configs/am43xx_evm_qspiboot_defconfig
+F:	configs/am43xx_evm_usbhost_boot_defconfig
+F:	configs/am43xx_evm_rtconly_defconfig
+F:	configs/am43xx_hs_evm_defconfig
diff --git a/board/mycompany/myboard/Makefile b/board/mycompany/myboard/Makefile
new file mode 100644
index 00000000000..b618f632eff
--- /dev/null
+++ b/board/mycompany/myboard/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
+
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/mycompany/myboard/board.c b/board/mycompany/myboard/board.c
new file mode 100644
index 00000000000..71320e7d895
--- /dev/null
+++ b/board/mycompany/myboard/board.c
@@ -0,0 +1,796 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <linux/errno.h>
+#include <spl.h>
+#include <usb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include "board.h"
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include <power/tps62362.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+	{	/* 19.2 MHz */
+		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
+		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 24 MHz */
+		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 25 MHz */
+		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 26 MHz */
+		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
+		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
+		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
+		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
+		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
+		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
+		{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
+		{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
+		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+		50, 2, 1, -1, 2, -1, -1};
+
+static const struct dpll_params idk_dpll_ddr = {
+	400, 23, 1, -1, 2, -1, -1
+};
+
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+	.sdram_config			= 0x808012BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0xEA86B411,
+	.sdram_tim2			= 0x103A094A,
+	.sdram_tim3			= 0x0F6BA37F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E284006,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config			= 0x000FFFFF
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0xc163,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x00048008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413b2,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0e084008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x89,
+	.emif_ddr_ext_phy_ctrl_3	= 0x90,
+	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
+	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x80000000,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
+	.sdram_config			= 0x61a11b32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1		= 0x00008009,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000405,
+	.emif_prio_class_serv_map	= 0x00000000,
+	.emif_connect_id_serv_1_map	= 0x00000000,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x00ffffff
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+		return &gp_evm_dpll_ddr;
+}
+
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	int opp, offset, i;
+
+	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
+
+	for (i = max_off; i >= min_off; i--) {
+		offset = opp & (1 << i);
+		if (!offset)
+			return i;
+	}
+
+	return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+	u32 ind = get_sys_clk_index();
+
+	return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_per[ind];
+}
+
+void scale_vcores_generic(u32 m)
+{
+	int mpu_vdd, ddr_volt;
+
+	if (power_tps65218_init(0))
+		return;
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+
+	/* Set DCDC1 (CORE) voltage to 1.1V */
+	if (tps65218_voltage_update(TPS65218_DCDC1,
+				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+
+	ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
+
+	/* Set DCDC3 (DDR) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+
+void scale_vcores_idk(u32 m)
+{
+	int mpu_vdd;
+
+	if (power_tps62362_init(0))
+		return;
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+	/* Set VDD_MPU voltage */
+	if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+void gpi2c_init(void)
+{
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+		first_time = false;
+	}
+}
+
+void scale_vcores(void)
+{
+	const struct dpll_params *mpu_params;
+
+	/* Ensure I2C is initialized for PMIC configuration */
+	gpi2c_init();
+
+	/* Get the frequency */
+	mpu_params = get_dpll_mpu_params();
+
+	scale_vcores_generic(mpu_params->m);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+static void enable_vtt_regulator(void)
+{
+	u32 temp;
+
+	/* enable module */
+	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+	/* enable output for GPIO5_7 */
+	writel(GPIO_SETDATAOUT(7),
+	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(GPIO_OE_ENABLE(7));
+	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
+enum {
+	RTC_BOARD_EPOS = 1,
+	RTC_BOARD_EVM14,
+	RTC_BOARD_EVM12,
+	RTC_BOARD_GPEVM,
+	RTC_BOARD_SK,
+};
+
+/*
+ * In the rtc_only+DRR in self-refresh boot path we have the board type info
+ * in the rtc scratch pad register hence we bypass the costly i2c reads to
+ * eeprom and directly programthe board name string
+ */
+void rtc_only_update_board_type(u32 btype)
+{
+	const char *name = "";
+	const char *rev = "1.0";
+
+	switch (btype) {
+	case RTC_BOARD_EPOS:
+		name = "AM43EPOS";
+		break;
+	case RTC_BOARD_EVM14:
+		name = "AM43__GP";
+		rev = "1.4";
+		break;
+	case RTC_BOARD_EVM12:
+		name = "AM43__GP";
+		rev = "1.2";
+		break;
+	case RTC_BOARD_GPEVM:
+		name = "AM43__GP";
+		break;
+	case RTC_BOARD_SK:
+		name = "AM43__SK";
+		break;
+	}
+	ti_i2c_eeprom_am_set(name, rev);
+}
+
+u32 rtc_only_get_board_type(void)
+{
+
+	return 0;
+}
+
+void sdram_init(void)
+{
+
+	/* GP EVM has 1GB DDR3 connected to EMIF along with VTT regulator */
+	enable_vtt_regulator();
+	config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			&ddr3_emif_regs_400Mhz_production, 0);
+}
+#endif
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+    int rc;
+
+    rc = power_tps65218_init(0);
+    if (rc) {
+        printf("Failed to initialize TPS65218 PMIC: %d\n", rc);
+        return rc;
+    }
+
+    puts("PMIC:  TPS65218\n");
+
+    return 0;
+}
+
+int board_init(void)
+{
+	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+	    modena_init0_bw_integer, modena_init0_watermark_0;
+
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	/*
+	 * Call this to initialize *ctrl again
+	 */
+	hw_data_init();
+
+	/* Clear all important bits for DSS errata that may need to be tweaked*/
+	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+	                   MREQPRIO_0_SAB_INIT0_MASK;
+
+	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+	                                   BW_LIMITER_BW_FRAC_MASK;
+
+	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+	                                BW_LIMITER_BW_INT_MASK;
+
+	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+	                                 BW_LIMITER_BW_WATERMARK_MASK;
+
+	/* Setting MReq Priority of the DSS*/
+	mreqprio_0 |= 0x77;
+
+	/*
+	 * Set L3 Fast Configuration Register
+	 * Limiting bandwith for ARM core to 700 MBPS
+	 */
+	modena_init0_bw_fractional |= 0x10;
+	modena_init0_bw_integer |= 0x3;
+
+	writel(mreqprio_0, &cdev->mreqprio_0);
+	writel(mreqprio_1, &cdev->mreqprio_1);
+
+	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		env_set("boot_fit", "1");
+#endif
+
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3@48380000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3@483c0000"))
+		enable_usb_clocks(1);
+#endif
+
+	/* Just probe the potentially supported cdce913 device */
+	uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
+
+	return 0;
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss1 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS1_BASE,
+	.tx_fifo_resize = false,
+	.index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss1_glue = {
+	.base = (void *)USB_OTG_SS1_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy1_device = {
+	.usb2_phy_power = (void *)USB2_PHY1_POWER,
+	.index = 0,
+};
+
+static struct dwc3_device usb_otg_ss2 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS2_BASE,
+	.tx_fifo_resize = false,
+	.index = 1,
+};
+
+static struct dwc3_omap_device usb_otg_ss2_glue = {
+	.base = (void *)USB_OTG_SS2_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 1,
+};
+
+static struct ti_usb_phy_device usb_phy2_device = {
+	.usb2_phy_power = (void *)USB2_PHY2_POWER,
+	.index = 1,
+};
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(dev);
+	if (status)
+		dwc3_uboot_handle_interrupt(dev);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
+	switch (index) {
+	case 0:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+			ti_usb_phy_uboot_init(&usb_phy1_device);
+			dwc3_uboot_init(&usb_otg_ss1);
+		}
+		break;
+	case 1:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
+		}
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+#endif
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+#ifdef CONFIG_USB_DWC3
+	switch (index) {
+	case 0:
+	case 1:
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+#endif
+	disable_usb_clocks(index);
+
+	return 0;
+}
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
+int board_fit_config_name_match(const char *name)
+{
+		return 0;
+}
+#endif
+
+#ifdef CONFIG_DTB_RESELECT
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
+void am33xx_spl_board_init(void)
+{
+    /* Mux UART0 pins for early debug */
+    enable_uart0_pin_mux();
+
+    /* Test print */
+    puts(">>> MYBOARD: Hello from SPL!\n");
+
+    /* Add any early DDR init, PMIC setup, etc. */
+}
diff --git a/board/mycompany/myboard/board.h b/board/mycompany/myboard/board.h
new file mode 100644
index 00000000000..37a169aaf75
--- /dev/null
+++ b/board/mycompany/myboard/board.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <asm/arch/omap.h>
+
+#define DEV_ATTR_MAX_OFFSET    5
+#define DEV_ATTR_MIN_OFFSET    0
+
+static inline int board_is_eposevm(void)
+{
+	return board_ti_is("AM43EPOS");
+}
+
+static inline int board_is_gpevm(void)
+{
+	return board_ti_is("AM43__GP");
+}
+
+static inline int board_is_sk(void)
+{
+	return board_ti_is("AM43__SK");
+}
+
+static inline int board_is_idk(void)
+{
+	return board_ti_is("AM43_IDK");
+}
+
+static inline int board_is_hsevm(void)
+{
+	return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+	return board_is_gpevm() || board_is_hsevm();
+}
+
+static inline int board_is_evm_14_or_later(void)
+{
+	return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
+}
+
+static inline int board_is_evm_12_or_later(void)
+{
+	return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
+}
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+#endif
diff --git a/board/mycompany/myboard/mux.c b/board/mycompany/myboard/mux.c
new file mode 100644
index 00000000000..d1d792680bd
--- /dev/null
+++ b/board/mycompany/myboard/mux.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},	/* GPIO5_7 */
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+	{OFFSET(gpmc_wait0),	(MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},	/* Write Protect */
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},	/* Chip-Select */
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+	{-1},
+};
+#endif
+
+static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
+	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
+	configure_module_pin_mux(uart0_pin_mux);	
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 1fb791631da..8be2d47737a 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -713,6 +713,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 
 	if (CONFIG_IS_ENABLED(BOARD_INIT))
 		spl_board_init();
+	
+	am33xx_spl_board_init();
+
 
 	if (IS_ENABLED(CONFIG_SPL_WATCHDOG) && CONFIG_IS_ENABLED(WDT))
 		initr_watchdog();
diff --git a/configs/am43xx_myboard_defconfig b/configs/am43xx_myboard_defconfig
new file mode 100644
index 00000000000..1b9d64f4458
--- /dev/null
+++ b/configs/am43xx_myboard_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-myboard"
+CONFIG_AM43XX=y
+CONFIG_TARGET_AM43XX_MYBOARD=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_MISC_INIT_R is not set
+CONFIG_SPL_MAX_SIZE=0x439e0
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_ETH=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x300000
+CONFIG_SPL_FALCON_BOOT_MMCSD=y
+CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x00100000
+CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_RX_ETH_BUFFER=64
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_OMAP_USB2_PHY=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/generated_defconfig b/generated_defconfig
new file mode 100644
index 00000000000..5a59c5e4651
--- /dev/null
+++ b/generated_defconfig
@@ -0,0 +1,113 @@
+# 1 "./arch/../configs/am43xx_myboard_defconfig"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "./arch/../configs/am43xx_myboard_defconfig"
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-myboard"
+CONFIG_AM43XX=y
+CONFIG_TARGET_AM43XX_MYBOARD=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_MISC_INIT_R is not set
+CONFIG_SPL_MAX_SIZE=0x439e0
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_ETH=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x300000
+CONFIG_SPL_FALCON_BOOT_MMCSD=y
+CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x00100000
+CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_RX_ETH_BUFFER=64
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_OMAP_USB2_PHY=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
+CONFIG_SPL_USB_ETHER=y
diff --git a/include/configs/am43xx_myboard.h b/include/configs/am43xx_myboard.h
new file mode 100644
index 00000000000..dce40d41526
--- /dev/null
+++ b/include/configs/am43xx_myboard.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_AM43XX_EVM_H
+#define __CONFIG_AM43XX_EVM_H
+
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CFG_SYS_NS16550_CLK		48000000
+
+/* Enabling L2 Cache */
+#define CFG_SYS_PL310_BASE	0x48242000
+
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f.  This is taken care of in
+ * s_init when we have SPL used.
+ */
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_omap.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* NS16550 Configuration */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+
+#ifndef CONFIG_SPL_BUILD
+/* USB Device Firmware Update support */
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_QSPI_XIP
+#else
+#define DFUARGS
+#endif
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(NAND, nand, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef CONFIG_SPL_BUILD
+#include <env/ti/dfu.h>
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"fdtfile=undefined\0" \
+	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43XXHS; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43__SK; then " \
+			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
+		"if test $board_name = AM43_IDK; then " \
+			"setenv fdtfile am437x-idk-evm.dtb; fi; " \
+		"if test $board_name = MYBOARD; then " \
+			 "setenv fdtfile am437x-myboard.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0" \
+	NANDARGS \
+	NETARGS \
+	DFUARGS \
+	BOOTENV
+
+#endif
+
+#define PHY_ANEG_TIMEOUT	8000 /* PHY needs longer aneg time at 1G */
+
+/* NAND support */
+#ifdef CONFIG_MTD_RAW_NAND
+/* NAND: device related configs */
+/* NAND: driver related configs */
+#define CFG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	26
+#define NANDARGS \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
+	"nandrootfstype=ubifs rootwait\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#define NANDBOOT			"run nandboot; "
+#else /* !CONFIG_MTD_RAW_NAND */
+#define NANDARGS
+#define NANDBOOT
+#endif /* CONFIG_MTD_RAW_NAND */
+
+#if defined(CONFIG_TI_SECURE_DEVICE)
+/* Avoid relocating onto firewalled area at end of DRAM */
+#define CFG_PRAM (64 * 1024)
+#endif /* CONFIG_TI_SECURE_DEVICE */
+
+#endif	/* __CONFIG_AM43XX_EVM_H */
-- 
2.25.1

Souce details:

Repo : git.ti.com/.../ti-u-boot.git

Branch : ti-u-boot-2024.04

I’ve applied the attached patch and attempted to build and run the resulting image.

Could you please take a look and help me verify if I’m missing any essential initialization steps?
At the very least, I’d like to get the MLO (SPL) booting successfully.

Let me know if there's anything I might have done incorrectly or anything that needs to be added to ensure proper initialization.

Also the MLO file is generated is size of 154K.

Thanks in advance!

To debug the issue - no SPL booting message at all, I'd recommend enabling JTAG on your board to help debugging.
Best,
-Hong