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SYS/BIOS for the 28x "zero latency interrupts".

Steve Runion
Intellectual 960 points
Other Parts Discussed in Thread: SYSBIOS, TMS320F28335

Per http://processors.wiki.ti.com/index.php/SYS/BIOS_for_the_28x#Handling_28x_Interrupts_with_SYS.2FBIOS we are trying to improve the response time of our ADC HWI on the TMS32028335. The HWI is mapped to PIE group 1 interrrupt 1 and according to the link the appropriate mask to make the HWI a zero latency interrupt is 0x01.

 

 

However, when compiling I get the error "Hwi 32 conflicts with IER Mask 0x1". Can anyone direct me to further documentation (other than the link above) that describes the hardware specific features of BIOS for my processor or otherwise give an explanation on why my HWI cannot be configured as "zero latency"?

  • 0
    TI__Mastermind 22025 points

    Hi Steve,

    I discussed your issue with our BIOS experts and we think we know what the problem is.  The issue is that you used the GUI to define your ADC_HWI, doing so and setting the zero latency IER mask are incompatable settings.

    To fix the issue simply remove ADC_HWI from the GUI configuration tool and use Hwi.plugMeta() or Hwi_plug() to register your ADC interrupt function in the PIE.  This should remove your interrupt from the BIOS dispatcher and significantly decrease interrupt latency.  Check out the SYSBIOS API reference in the CCS help for more information.

    Trey

  • 0 in reply to Trey German289
    Intellectual 960 points

    So what you are saying is the HWI's are not compatible with the "zero latency" interrupts?

    I was under the impression, based on the wiki, is that the "zero latency" interrupts were some special class of BIOS HWI's who's latency could be reduced, while still using the dispatcher, under the assumption that they would never be disabled.

    Is there documentation anywhere that describes these "zero latency" interrupts in detail? We were hoping to post semaphores and SWI's from our HWI, and if the low latency things are not BIOS compatible then it sounds like we need to rethink our design.

  • 0 in reply to Steve Runion
    TI__Mastermind 30830 points

    Steve,

    Zero latency interrupts are not managed by the SYS/BIOS interrupt dispatcher and for most purposes behave like non-maskable interrupts.

    Consequently ISRs associated with them CAN NOT interact with BIOS objects due to critical code section requirements.

    This means you CAN NOT post Semaphores, Swis, or Events from them.

    The wiki article your referenced mentions these limitations (albeit rather obscurely) in section 3.3.

    The CDOC for the c28 Hwi module:

        http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_33_00_19/exports/bios_6_33_00_19/docs/cdoc/ti/sysbios/family/c28/Hwi.html

    discusses Zero latency interrupt support in the module level paragraphs, and in more detail in the zeroLatencyIERMask documentation.

    Alan

  • 0 in reply to Alan DeMars
    Intellectual 960 points
    Alan, Thanks for the link to the documentation. Steve
  • 0 in reply to Steve Runion
    Intellectual 960 points

    Question: How would I get to the link you sent me had I manually navigated from the C2000 http://www.ti.com/product/tms320f28335 page? This documentation is not necessarily intuitive to find.

  • 0 in reply to Steve Runion
    TI__Mastermind 30830 points

    The link I provided was from the SYS/BIOS CDOC repository that resides in your SYS/BIOS installation.

    You can browse the CDOCs for a particular SYS/BIOS release prior to downloading and installing it by first clicking on the SYS/BIOS version from the SYS/BIOS 6.x Product Download page:

        http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/index.html

    And then clicking on the 'Cdoc' link within that version's "Product Download Page".

    Alan

  • 0 in reply to Alan DeMars
    Intellectual 650 points

    My SysBios project is taking 390 cycle to service an interrupt.  I am still working through the mechanics of zeroLatencyIERMas and need some assistance. I read over this post, interpreted, and have changed to my working code accordingly. The changes below compile fine, but the mcu never enters into the interrupt function. Please offer some insight into what else needs to be done.  I suspect step 4 is incomplete.

    Step 1. Removed calls to Hwi.create() in *.cfg, since these are created through the "GUI" as Trey said.

    Step 2. Add line Hwi.zeroLatencyIERMask = 512; to *.cfg file.  This will enable interrupts in group 10, which contains all ADCINT for my device.

    Step 3. Import library #include <ti/sysbios/family/c28/Hwi.h> which includes Hwi_plug and Hwi_PlugFuncPtr

    Step 4. In my adc initialization function I manually "plug" my interrupt function, isr_adc_eoc.
    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;
    Hwi_plug(104, (Hwi_PlugFuncPtr)isr_adc_eoc);
    PieCtrlRegs.PIEIER10.bit; // Enable Group 10 in the PIE
    IER |= M_INT1;            // Enable CPU Interrupt 1
    EINT;                     // Enable Global interrupt INTM
    ERTM;                     // Enable Global realtime interrupt DBGM

    Step 5. Inside isr_adc_eoc, acknowledge the PIE.
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

  • 0 in reply to Grant E Pitel
    Intellectual 960 points

    I am new at this myself. However, shouldn't "PieCtrlRegs.PIEIER10.bit;" be something more like PieCtrlRegs.PIEIER10.bit.INTx1 = 1;"?