AM6442: Enabling and Receiving IEP0 Compare Event Interrupts on Linux

Tool/software:

Hi,

I am working enabling and routing the ICSSG1 IEP0 compare event interrupt (PRU_ICSSG1_PR1_IEP0_CMP_INTR_REQ_0) to Linux running on A53 compute cluster. I believe I have set up the IEP0 and compare event registers correctly; however, Linux is still not seeing the interrupt (at least /proc/interrupts is indicates such).

To configure the compare interrupt router to route PRU_ICSSG1_PR1_IEP0_CMP_INTR_REQ_0 to GICSS0_SPI_IN_48, I have set modified the CMP_INTROUTER0_INTR_MUXCNTL register via the following modifications to the DTS:

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index f585eda7fa16..00ad21cf1049 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -754,6 +754,14 @@ main_cpts0: cpts@39000000 {
 		ti,cpts-ext-ts-inputs = <8>;
 	};
 
+	cmp_event_router: cmp-event-router@a30000 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0xa30000 0x0 0x800>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0001007f>;
+	};
+
 	timesync_router: pinctrl@a40000 {
 		compatible = "pinctrl-single";
 		reg = <0x0 0xa40000 0x0 0x800>;
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 0e1447b382ee..98de61704abe 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -429,3 +429,17 @@ adc {
 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
 	};
 };
+
+/* 
+ * compare event routing 
+ *  desc: route CMPEVENT_INTRTR0 PRU_ICSSG1_PR1_IEP0_CMP_INTR_REQ_0 => GIC CMPEVENT_INTROUTER0_OUTP_0
+ *  see: AM6442 TRMr2 (Table 9-60, Table 9-71, Table Table 10-133)
+ */
+&cmp_event_router {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pru_iep_interrupt>;
+
+    pru_iep_interrupt: pru-iep-interrupt {
+        pinctrl-single,pins = <0x00000004 0x00010030>;
+    };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 98de61704abe..6d9b91bfa6e5 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -134,6 +134,8 @@ jailhouse_mem: jailhouse@dfa00000 {
   	apc {
  		compatible = "apc-memory";
  		memory-region = <&apc_memory_region>;
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  	};

Note that compare interrupt 48 is mapped to ICSSG0 IEP0 compare event 0 and GICSS0 SPI interrupt 48 is mapped to compare event router output 0. This device tree modification seems to work, and I successfully request the interrupt in my kernel module. This is all verified by the fact that I see the following in /proc/interrupts:

547:          0          0     GICv3  48 Level     apc

I have also configured the ICSS1 IEP0 registers to enable and configure compare event 0. I am pretty confident that I have configured this compare event correctly as I can see the compare event status bit status set and reset as expected (I am viewing this via looking at the IEP_CMP_STATUS_REG register).

QUESTIONS:

1. Is there anything glaringly wrong with my approach?
2. Are any modifications to the PRU's INTC required for proper routing of the IEP0 compare interrupt to the GIC?

Really appreciate the help,

- Jared