AM623: GPMC_FCLK and GPMC_CLK configuration

Koichiro Tashiro

Part Number: AM623

Tool/software:

Hi,

My customer wants to set GPMC_CLK frequency as 64MHz.
It seems only possible GPMC_FCLK is 133MHz or 100MHz and GPMCFCLKDIVIDER allows 1/2, 1/3 or 1/4 only.
So possible configurations are below.

GPMC_FCLK	1/1	1/2	1/3	1/4
133MHz	133MHz	66.5MHz	44.3MHz	33.25MHz
100MHz	100MHz	50MHz	33.3MHz	25MHz

Q1) Above assumptions are correct?
Q2) Is it possible to change GPMC_FCLK other than 133MHz or 100MHz?
For example, setting PLL2 hsdiv_clkout7 to 1/16 and supply 62.5MHz to GPMC_FCLK works without any impacts to other modules?

Thanks and regards,
Koichiro Tashiro

2 months ago

0 Stanislav Stilyanov 2 months ago

TI__Mastermind 18420 points

Hi Koichiro-san,

For Q1, yes with a small remark - the 133 MHz clock is more precisely equal to 133.3 MHz as you can see on your screenshot, making the divided results slightly different - 66.7 | 44.4 | 33.3 . I presume it is not that important for you though.

For Q2, I didn't find any other module or peripheral that relies on this clock. So yes, I see no reason not to use MAIN_PLL2_HSDIV7_CLKOUT for GPMC.

Regards,

Stan

0 Koichiro Tashiro 2 months ago in reply to Stanislav Stilyanov

TI__Mastermind 22935 points

Hi Stan,

Thanks for your quick reply.
For Q2, GPMC itself can work with 62.5MHz?
I have a concern GPMC was designed and validated only for 133MHz and 100MHz.

Thanks and regards,
Koichiro Tashiro

0 Koichiro Tashiro 2 months ago in reply to Koichiro Tashiro

TI__Mastermind 22935 points

Hi Stan,

Could you reply to my last question?

Thanks and regards,
Koichiro Tashiro

0 Stanislav Stilyanov 2 months ago in reply to Koichiro Tashiro

TI__Mastermind 18420 points

Hi Koichiro-san,

I got the following feedback from GPMC expert:

"Hi Stan, we have not validated changing PLL to get specific GPMC frequencies. It should be fine if the frequency can be achieved by changing only the HSDIV (assuming no other peripheral shares the same HSDIV output clock)."

Regards,

Stan

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AM623: GPMC_FCLK and GPMC_CLK configuration