McBSP Configuration for TI AIC3106 codec

Soon Toong Pua

Other Parts Discussed in Thread: OMAPL138

Hi,

I am working on TWO AIC3106 codecs which using the McASP and McBSP1 port for C6748 processor (OMAPL138 board) for two independent audio channel processing.

McASP work fine from the PSP package examples given under audiosample, however the McBSP1 (original from PSP's mcbspSampleSlave examples) wasn't when interfacing with another AIC31 codec, the CPU loading always high and keep pooling at Mcbsp_swiTxFifo() when tracing. This cause the output audio quality distortion.

I will be very appreciate if anyone who can provide me with a example for McBSP1 interface with AIC31 codec or its configuration with the TI codec.

Here my current McBSP1 configuration:

////////////////////////////////


/**< settings to configure the TX or RX hardware sections                 */
Mcbsp_DataConfig mcbspTxChanConfig =
{
    Mcbsp_Phase_SINGLE,
    Mcbsp_WordLength_32,
    Mcbsp_WordLength_32,    /* Dont care for single phase*/
    NUM_OF_CHANNELS,
    NUM_OF_CHANNELS,       /* Dont care for single phase*/
    Mcbsp_FrmSync_DETECT,
    Mcbsp_DataDelay_0_BIT,
    Mcbsp_Compand_OFF_MSB_FIRST,
    Mcbsp_BitReversal_DISABLE,
    Mcbsp_IntMode_ON_READY,
    Mcbsp_RxJust_RZF,  /* Dont care for TX         */
    Mcbsp_DxEna_OFF
};

/**< settings to configure the TX or RX hardware sections                 */
Mcbsp_DataConfig mcbspRxChanConfig =
{
    Mcbsp_Phase_SINGLE,
    Mcbsp_WordLength_32,
    Mcbsp_WordLength_32,     /* Dont care                */
    NUM_OF_CHANNELS,
    NUM_OF_CHANNELS,        /* Dont care                */
    Mcbsp_FrmSync_DETECT,
    Mcbsp_DataDelay_0_BIT,
    Mcbsp_Compand_OFF_MSB_FIRST,
    Mcbsp_BitReversal_DISABLE,
    Mcbsp_IntMode_ON_READY,
    Mcbsp_RxJust_RZF,   /* Dont care for TX         */
    Mcbsp_DxEna_OFF
};
/**< clock setup for the TX section                     */
Mcbsp_ClkSetup mcbspTxClkConfig =
{
    Mcbsp_FsClkMode_EXTERNAL,//Mcbsp_FsClkMode_INTERNAL,	/* internal clock for master */
    MCBSP_SAMPLE_RATE,                   /* 8KHz                   */
    Mcbsp_TxRxClkMode_EXTERNAL,//Mcbsp_TxRxClkMode_INTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_RISING_EDGE
};


/**< clock setup for the RX or the TX section                             */
Mcbsp_ClkSetup mcbspRxClkConfig =
{
    Mcbsp_FsClkMode_EXTERNAL,
    MCBSP_SAMPLE_RATE,                   /* 8KHz                   */
    Mcbsp_TxRxClkMode_EXTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_RISING_EDGE,
};

/**< Multi channel setup                                                      */
Mcbsp_McrSetup mcbspTxMultiChanCtrl =
{
    Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED,
    Mcbsp_PartitionMode_CHAN_0_15,
    Mcbsp_PartitionMode_CHAN_16_31,
    Mcbsp_PartitionMode_2
};

/**< Multi channel setup                                                  */
Mcbsp_McrSetup mcbspRxMultiChanCtrl =
{
    Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED,
    Mcbsp_PartitionMode_CHAN_0_15,
    Mcbsp_PartitionMode_CHAN_16_31,
    Mcbsp_PartitionMode_2
};

Mcbsp_ChanParams mcbspTxChanparam =
{
    Mcbsp_WordLength_32,   /* wordlength configured    */
    NULL,                 /* loop job buffer internal */
    0,                    /* user loopjob length      */
    NULL,                 /* global error callback    */
    NULL,                 /* edma Handle              */
    (0u),				  /* EDMA event queue         */
    10,/*8,*/                    /* hwi number               */
    Mcbsp_BufferFormat_1SLOT,
    TRUE,                 /* FIFO mode enabled        */
    &mcbspTxChanConfig,     /* channel configuration    */
    &mcbspTxClkConfig,      /* clock configuration      */
    &mcbspTxMultiChanCtrl,  /* multi channel control    */
    0x00,
    0x00,
    0x00,
    0x00
};


Mcbsp_ChanParams mcbspRxChanparam =
{
    Mcbsp_WordLength_32,   /* wordlength configured    */
    NULL,                 /* loop job buffer internal */
    0,                    /* user loopjob length      */
    NULL,                 /* global error callback    */
    NULL,                 /* edma Handle              */
    (1u),	              /* EDMA event queue         */
    9,                    /* hwi number               */
    Mcbsp_BufferFormat_1SLOT,
    TRUE,                 /* FIFO mode enabled        */
    &mcbspRxChanConfig,     /* channel configuration    */
    &mcbspRxClkConfig,      /* clock configuration      */
    &mcbspRxMultiChanCtrl,  /* multi channel control    */
    0x00,
    0x00,
    0x00,
    0x00
};

///////////////////////////////////////////////

Thanks in advance,

PST

over 13 years ago

0 Joe Coombs over 13 years ago

TI__Expert 8890 points

PST,

Sorry for my delay in responding. One thing that I notice in your code is that both McBSP channels (receive and transmit) have the clock and frame sync sources configured as external (i.e. in the Mcbsp_ClkSetup structs). Are you generating the clock and frame sync with some other device or peripheral, like McASP? If not, that may be why the McBSP seems unresponsive.

Hope this helps.

0 Soon Toong Pua over 13 years ago in reply to Joe Coombs

Prodigy 40 points

Hi Joe,

Thanks for reply. In fact we were able to get it working last week by recompiled the mcbsp library with Mcbsp_LOOPJOB_ENABLE defined and better tx/rx buffers prime, also set FIFO mode disable (enable might be work, will try). Though I am not very sure what Mcbsp_LOOPJOB_ENABLE actually does but it works now with two audio channel McASP/McBSP running independently.

Another question while debugging and configuring the McBSP audio interface (refer to BIOSPSP_AudioInterface_Driver_Design.pdf), though the driver mentioned it supports McBSP interface as well (Figure 1) but from the audio library (pspiom/platform/evmOMAPL138/audio) after defining new audio device drivers through BIOS configuration tool for McBSP1 audio interface, it would return error at below Audio.c code

retVal = ((IOM_Fxns *)instHandle->adDevHandle->

fxns)->mdControlChan(

chanHandle->aiAudioChanHandle,

Mcasp_IOCTL_GET_DEVINFO,

(Ptr)&instHandle->adAudioDevData);

Obviously the PSP audio driver only supports McASP at the moments, in any case we bypassed this section and still works for McBSP now. You may give more info about these section or future driver update.

Thank you very much!

PST

0 Soon Toong Pua over 13 years ago in reply to Soon Toong Pua

Prodigy 40 points

Oh ya, for your question regarding clock and frame sync.

Yes, McBSP is slave interface with another AIC31 codec, like McASP with external clk, frame sync (8/16kHz sampling rate).

rgds,

PST

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McBSP Configuration for TI AIC3106 codec