AM625: can not receive any data from mipi

lion chen

Part Number: AM625

Tool/software:

We are using an FPGA chip connected to the MIPI CSI2 clock lane and 4 data lanes of an AM625. The FPGA starts sending MIPI data immediately after loading the bitstream, with the format being 640x480, YVYU8_1X16 (data type 0x1e) and a link frequency of 400MHz. After Linux boots, we load the imx459 driver, which includes some code for configuring the ov5640 for testing on an AM62B-P1 motherboard with a camera. Testing uses the same resolution and format, and MIPI data can be obtained normally in this configuration.

When the driver is ported to our project motherboard, it can successfully create v4l-dev, videoX, and mediaX devices without reporting any errors, but MIPI data cannot be obtained. The topology is as follows:

	Media controller API version 6.6.58

	Media device information
	------------------------
	driver          j721e-csi2rx
	model           TI-CSI2RX
	serial          
	bus info        platform:30102000.ticsi2rx
	hw revision     0x1
	driver version  6.6.58

	Device topology
	- entity 1: 30102000.ticsi2rx (5 pads, 5 links, 1 route)
		    type V4L2 subdev subtype Unknown flags 0
		    device node name /dev/v4l-subdev0
		routes:
			0/0 -> 1/0 [ACTIVE]
		pad0: Sink
			[stream:0 fmt:YVYU8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
			<- "cdns_csi2rx.30101000.csi-bridge":1 [ENABLED,IMMUTABLE]
		pad1: Source
			[stream:0 fmt:YVYU8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
			-> "30102000.ticsi2rx context 0":0 [ENABLED,IMMUTABLE]
		pad2: Source
			-> "30102000.ticsi2rx context 1":0 [ENABLED,IMMUTABLE]
		pad3: Source
			-> "30102000.ticsi2rx context 2":0 [ENABLED,IMMUTABLE]
		pad4: Source
			-> "30102000.ticsi2rx context 3":0 [ENABLED,IMMUTABLE]

	- entity 7: cdns_csi2rx.30101000.csi-bridge (5 pads, 2 links, 1 route)
		    type V4L2 subdev subtype Unknown flags 0
		    device node name /dev/v4l-subdev1
		routes:
			0/0 -> 1/0 [ACTIVE]
		pad0: Sink
			[stream:0 fmt:YVYU8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
			<- "imx459 spi1.0":0 [ENABLED,IMMUTABLE]
		pad1: Source
			[stream:0 fmt:YVYU8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
			-> "30102000.ticsi2rx":0 [ENABLED,IMMUTABLE]
		pad2: Source
		pad3: Source
		pad4: Source

	- entity 13: imx459 spi1.0 (1 pad, 1 link, 0 routes)
		     type V4L2 subdev subtype Sensor flags 0
		     device node name /dev/v4l-subdev2
		pad0: Source
			[stream:0 fmt:Y8_1X8/640x480 field:none colorspace:raw xfer:none ycbcr:601 quantization:full-range]
			-> "cdns_csi2rx.30101000.csi-bridge":0 [ENABLED,IMMUTABLE]

	- entity 19: 30102000.ticsi2rx context 0 (1 pad, 1 link)
		     type Node subtype V4L flags 0
		     device node name /dev/video0
		pad0: Sink
			<- "30102000.ticsi2rx":1 [ENABLED,IMMUTABLE]

	- entity 25: 30102000.ticsi2rx context 1 (1 pad, 1 link)
		     type Node subtype V4L flags 0
		     device node name /dev/video1
		pad0: Sink
			<- "30102000.ticsi2rx":2 [ENABLED,IMMUTABLE]

	- entity 31: 30102000.ticsi2rx context 2 (1 pad, 1 link)
		     type Node subtype V4L flags 0
		     device node name /dev/video2
		pad0: Sink
			<- "30102000.ticsi2rx":3 [ENABLED,IMMUTABLE]

	- entity 37: 30102000.ticsi2rx context 3 (1 pad, 1 link)
		     type Node subtype V4L flags 0
		     device node name /dev/video3
		pad0: Sink
			<- "30102000.ticsi2rx":4 [ENABLED,IMMUTABLE]

The following commands are used for testing

	v4l2-ctl --verbose -d /dev/video0 --set-fmt-video=width=640,height=480,pixelformat=YVYU --stream-mmap=2 --stream-poll

Test results:

	VIDIOC_QUERYCAP: ok
	VIDIOC_G_FMT: ok
	VIDIOC_S_FMT: ok
	Format Video Capture:
		Width/Height      : 640/480
		Pixel Format      : 'YVYU' (YVYU 4:2:2)
		Field             : None
		Bytes per Line    : 1280
		Size Image        : 614400
		Colorspace        : sRGB
		Transfer Function : sRGB
		YCbCr/HSV Encoding: ITU-R 601
		Quantization      : Limited Range
		Flags             : 
			VIDIOC_REQBUFS returned 0 (Success)
			VIDIOC_QUERYBUF returned 0 (Success)
			VIDIOC_QUERYBUF returned 0 (Success)
			VIDIOC_G_FMT returned 0 (Success)
			VIDIOC_QBUF returned 0 (Success)
			VIDIOC_QBUF returned 0 (Success)
			VIDIOC_STREAMON returned 0 (Success)
	select timeout

Kernel register settings of enabling the stream:

	[   28.709864] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:322] write reg: 0x10, value: 0x1
	[   28.709870] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:325] read back: 0x10, value: 0xf01
	[   28.709875] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:322] write reg: 0x20, value: 0x8c00001e
	[   28.709880] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:325] read back: 0x20, value: 0x8c00001e
	[   28.709885] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:322] write reg: 0x24, value: 0x0
	[   28.709890] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:325] read back: 0x24, value: 0x0
	[   28.709899] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:850] sizeimage: 614400
	[   28.709931] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:850] sizeimage: 614400
	[   28.709966] j721e-csi2rx 30102000.ticsi2rx: enable streams 1:0x1
	[   28.709974] j721e-csi2rx 30102000.ticsi2rx: Enabling all streams (1) on sink.
	[   28.709993] j721e-csi2rx 30102000.ticsi2rx: enable streams 1:0x1
	[   28.710000] cdns-csi2rx 30101000.csi-bridge: enable streams
	[   28.710071] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x4, value: 0x3
	[   28.710078] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x4, value: 0x0
	[   28.710083] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x100, value: 0x10
	[   28.710088] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x100, value: 0x0
	[   28.710093] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x200, value: 0x10
	[   28.710098] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x200, value: 0x0
	[   28.710144] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x300, value: 0x10
	[   28.710150] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x300, value: 0x0
	[   28.710155] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x400, value: 0x10
	[   28.710159] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x400, value: 0x0
	[   28.710207] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x4, value: 0x0
	[   28.710215] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x4, value: 0x0
	[   28.710221] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x100, value: 0x0
	[   28.710226] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x100, value: 0x0
	[   28.710231] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x200, value: 0x0
	[   28.710235] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x200, value: 0x0
	[   28.710240] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x300, value: 0x0
	[   28.710245] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x300, value: 0x0
	[   28.710249] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x400, value: 0x0
	[   28.710254] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x400, value: 0x0
	[   28.710263] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x8, value: 0x43210400
	[   28.710268] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x8, value: 0x43210400
	[   28.710286] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x40, value: 0x1f01f
	[   28.710291] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x40, value: 0x1f01f
	[   28.710316] MIPI D-PHY: pixelclocl: 0, bpp: 0, lanes: 4, hs_clk_rate 750000000, ui: 1334
	[   28.710381] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0x20, value: 0x429
	[   28.710387] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0x20, value: 0x429
	[   28.710417] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0x1000, value: 0x800000
	[   28.710422] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0x1000, value: 0x800000
	[   28.710437] hs_clk_rate = 750000000, rate = 1500
	[   28.710448] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0xb00, value: 0x273
	[   28.710453] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0xb00, value: 0x273
	[   28.710460] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0xb08, value: 0xaaaaaaaa
	[   28.710465] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0xb08, value: 0xaaaaaaaa
	[   28.710470] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0xb0c, value: 0xaa
	[   28.710475] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0xb0c, value: 0xaa
	[   28.710787] [drivers/phy/cadence/cdns-dphy-rx.c:163] wait 0xc10 bit 0, ret: 0
	[   28.710797] [drivers/phy/cadence/cdns-dphy-rx.c:170] wait 0xc14 bit 0 lane 0, ret: 0
	[   28.710803] [drivers/phy/cadence/cdns-dphy-rx.c:170] wait 0xc20 bit 0 lane 1, ret: 0
	[   28.710809] [drivers/phy/cadence/cdns-dphy-rx.c:170] wait 0xc30 bit 0 lane 2, ret: 0
	[   28.710815] [drivers/phy/cadence/cdns-dphy-rx.c:170] wait 0xc3c bit 0 lane 3, ret: 0
	[   28.710892] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x10c, value: 0x100
	[   28.710898] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x10c, value: 0x100
	[   28.710903] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x108, value: 0x0
	[   28.710908] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x108, value: 0x0
	[   28.710913] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x100, value: 0x1
	[   28.710917] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x100, value: 0x1
	[   28.710923] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x20c, value: 0x100
	[   28.710928] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x20c, value: 0x100
	[   28.710932] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x208, value: 0x0
	[   28.710937] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x208, value: 0x0
	[   28.710941] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x200, value: 0x1
	[   28.710946] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x200, value: 0x0
	[   28.711001] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x30c, value: 0x100
	[   28.711007] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x30c, value: 0x100
	[   28.711012] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x308, value: 0x0
	[   28.711017] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x308, value: 0x0
	[   28.711022] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x300, value: 0x1
	[   28.711026] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x300, value: 0x1
	[   28.711031] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x40c, value: 0x100
	[   28.711036] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x40c, value: 0x100
	[   28.711041] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x408, value: 0x0
	[   28.711045] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x408, value: 0x0
	[   28.711050] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x400, value: 0x1
	[   28.711055] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x400, value: 0x1

Kernel registers settings of stopping the stream:

	[   30.715046] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:322] write reg: 0x10, value: 0x0
	[   30.715118] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:325] read back: 0x10, value: 0xf00
	[   30.715133] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:322] write reg: 0x20, value: 0x0
	[   30.715138] [drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c:325] read back: 0x20, value: 0x0
	[   30.715243] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x100, value: 0x2
	[   30.715250] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x100, value: 0x2
	[   30.715256] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x200, value: 0x2
	[   30.715261] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x200, value: 0x0
	[   30.715316] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x300, value: 0x2
	[   30.715321] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x300, value: 0x2
	[   30.715327] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x400, value: 0x2
	[   30.715332] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x400, value: 0x2
	[   30.715427] [drivers/media/platform/cadence/cdns-csi2rx.c:149] write reg: 0x40, value: 0x0
	[   30.715432] [drivers/media/platform/cadence/cdns-csi2rx.c:152] read back: 0x40, value: 0x0
	[   30.715439] [drivers/phy/cadence/cdns-dphy-rx.c:81] write reg: 0x20, value: 0x0
	[   30.715445] [drivers/phy/cadence/cdns-dphy-rx.c:84] read back: 0x20, value: 0x0

Currently observed issue:
After writing start/stop commands to stream1_ctrl, the status read back does not indicate the start/stop state change.

Status register values during operation:

	dphy status		: 0x333306d
	dphy error status	: 0x0
	integration debug	: 0x10000000
	error debug  		: 0x0
	stream0 status		: 0x80000111
	stream1 status 		: 0x80000011
	stream2 status 		: 0x80000111
	stream3 status 		: 0x80000111

2 months ago

0 Jianzhong Xu 2 months ago

TI__Guru 58915 points

Hi Lion,

lion chen said:
The FPGA starts sending MIPI data immediately after loading the bitstream, with the format being 640x480, YVYU8_1X16 (data type 0x1e) and a link frequency of 400MHz

Did you specify this link frequency in the device tree overlay, similar to https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso?h=ti-linux-6.1.y#n50. This information is needed to configure the D-PHY receiver on AM62.

Since your FPGA chip works with the AM62 board: https://www.ti.com/tool/SK-AM62B-P1, please double check your board and see if there are any differences with respect to CSI Rx between your board and TI's board.

Regards,

Jianzhong

0 lion chen 2 months ago in reply to Jianzhong Xu

Prodigy 30 points

Hi Jianzhong,

In the driver, we hardcoded the value of the link frequency without using the link-frequencies defined in the device tree to validate the link frequency being used. Additionally, we traced this parameter and found that it is ultimately assigned to hs_clk_rate and then configured in the register DPHY_BAND_CFG. We added logging to print the configured value and confirmed that it matches our setting.

	band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
	if (band_ctrl < 0)
		return band_ctrl;

	reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
	      FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
	writel(reg, dphy->regs + DPHY_BAND_CFG);

The differences compared to the AM62B0-P1 development board are as follows:

Number of data lanes:
- Our development board uses 4 data lanes, while the TI board uses 2 lanes.
Link frequency configuration:
- Our board is configured for 750 MHz, whereas the TI board uses 192 MHz.
Power supply to CSIRX:
- Our board supplies 1.8V to the CSIRX, which is a hardware design error.

Additionally, during testing yesterday, we noticed that when starting the stream via the stream_ctrl register, streams 0/2/4 work normally, but stream 1 fails to start. All other register configurations appear successful except for the stream_ctrl register. What could cause the stream_ctrl configuration to fail?

Regards,

Lion

0 Jianzhong Xu 2 months ago in reply to lion chen

TI__Guru 58915 points

lion chen said:
In the driver, we hardcoded the value of the link frequency without using the link-frequencies defined in the device tree to validate the link frequency being used.

This should be fine. Please check register 0x30110B00 and make sure bits [4:0] has the right value. If your link frequency is 750MHz, the data rate will be 1500MHz, and bits [4:0] of this register should have value 0x13. This means element 19 in this table: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/phy/cadence/cdns-dphy-rx.c?h=ti-linux-6.6.y#n72, { 1500, 1750 }.

Also, when your DPHY operates at 1.5Gbps lane speed, your DPHY Tx should send a deskew sequency so that the DPHY RX on the SoC is properly calibrated to receive data at 1.5Gbps.

What is the reason that you used 4 lanes and 750MHz instead of 2 lanes and 192MHz?

lion chen said:
Additionally, during testing yesterday, we noticed that when starting the stream via the stream_ctrl register, streams 0/2/4 work normally, but stream 1 fails to start.

Please keep in mind that streams do not map to lanes. Only stream 0 is used on AM62x. Please refer to the CSI Rx interface block diagram in the TRM:

Regards,

Jianzhong

0 jian wen 2 months ago in reply to Jianzhong Xu

Prodigy 130 points

Read at address 0x30110B00 (0xffff9b8b7b00): 0x00000273

Table 14-19546. ECC_AGGR_CFG, ECC_AGGR_CFG Registers
base = 0x0070e000
Read at address 0x0070E000 (0xffff884a9000): 0x66A02A01
Read at address 0x0070E008 (0xffff8c3cf008): 0x00000000
Read at address 0x0070E00C (0xffffb1edb00c): 0x00000008
Read at address 0x0070E010 (0xffffb7dbb010): 0x00000000
Read at address 0x0070E03C (0xffff83e9a03c): 0x00000000
Read at address 0x0070E040 (0xffffa80ad040): 0x00000000
Read at address 0x0070E080 (0xffffbf4ca080): 0x00000000
Read at address 0x0070E0C0 (0xffff965b30c0): 0x00000000
Read at address 0x0070E13C (0xffffbdccb13c): 0x00000000
Read at address 0x0070E140 (0xffff82222140): 0x00000000
Read at address 0x0070E180 (0xffff9f923180): 0x00000000
Read at address 0x0070E1C0 (0xffff949d71c0): 0x00000000
Read at address 0x0070E200 (0xffffb5617200): 0x00000000
Read at address 0x0070E204 (0xffffa35e3204): 0x00000000
Read at address 0x0070E208 (0xffffb40ab208): 0x00000000
Read at address 0x0070E20C (0xffffa8f2a20c): 0x00000000

Table 14-19547. CP_INTD_CFG_INTD_CFG, CP_INTD_CFG_INTD_CFG Registers
base = 0x30100000
Read at address 0x30100000 (0xffff98ad8000): 0x6690A200
Read at address 0x30100010 (0xffffb2d51010): 0x00000000
Read at address 0x30100014 (0xffffa0228014): 0x00000000
Read at address 0x30100100 (0xffff8595c100): 0x00000000
Read at address 0x30100104 (0xffffa2c4d104): 0x00000000
Read at address 0x30100300 (0xffff96990300): 0x00000000
Read at address 0x30100304 (0xffff8598d304): 0x00000000
Read at address 0x30100500 (0xffff8a03e500): 0x00000000
Read at address 0x30100504 (0xffffbb871504): 0x00000000
Read at address 0x30100700 (0xffffaea01700): 0x00000000
Read at address 0x30100704 (0xffff9844e704): 0x00000000
Read at address 0x30100A80 (0xffffbceaba80): 0x00000000
Read at address 0x30100A84 (0xffffb0aefa84): 0x00000000

Table 14-19548. VBUS2APB_WRAP_VBUSP_APB_CSI2RX, VBUS2APB_WRAP_VBUSP_APB_CSI2RX Registers
base = 0x30101000
Read at address 0x30101000 (0xffff8700f000): 0x8C63164C
Read at address 0x30101004 (0xffff8f654004): 0x00000000
Read at address 0x30101008 (0xffff8b56a008): 0x43210400
Read at address 0x30101010 (0xffffafd24010): 0x00000000
Read at address 0x30101018 (0xffff9ac28018): 0x00000000
Read at address 0x3010101C (0xffffa358d01c): 0x00000000
Read at address 0x30101020 (0xffffb5313020): 0x00000052
Read at address 0x30101024 (0xffffb316d024): 0x00000000
Read at address 0x30101028 (0xffffab29a028): 0x000009F0
Read at address 0x3010102C (0xffff9799302c): 0x00000000
Read at address 0x30101040 (0xffff9b0e4040): 0x0001F01F
Read at address 0x30101048 (0xffffa8ad9048): 0x00222206
Read at address 0x3010104C (0xffffa088c04c): 0x00000000
Read at address 0x30101050 (0xffffb583d050): 0x00000000
Read at address 0x30101060 (0xffffa301a060): 0x10888094
Read at address 0x30101074 (0xffffa5a4a074): 0x80140018
Read at address 0x30101080 (0xffff92f46080): 0x00000000
Read at address 0x30101100 (0xffff8fe02100): 0x00000001
Read at address 0x30101104 (0xffff93d35104): 0x80000111
Read at address 0x30101108 (0xffff82ceb108): 0x00030000
Read at address 0x3010110C (0xffff9415f10c): 0x00000100
Read at address 0x30101110 (0xffffa32a8110): 0x00000000
Read at address 0x30101114 (0xffffbb519114): 0x00000000
Read at address 0x30101118 (0xffffb9938118): 0x00000000
Read at address 0x3010111C (0xffffafb1811c): 0x00000000
Read at address 0x30101120 (0xffff9c6ea120): 0x00000000
Read at address 0x30101124 (0xffffb3315124): 0x00000000
Read at address 0x30101128 (0xffff832ca128): 0x00000000
Read at address 0x30101200 (0xffffa1150200): 0x00000000
Read at address 0x30101204 (0xffffa7961204): 0x80000011
Read at address 0x30101208 (0xffffbade9208): 0x00010000
Read at address 0x3010120C (0xffffa48bd20c): 0x00000100
Read at address 0x30101210 (0xffffb9268210): 0x00000000
Read at address 0x30101214 (0xffffaf54c214): 0x00000000
Read at address 0x30101218 (0xffff9c993218): 0x00000000
Read at address 0x3010121C (0xffffb8a8421c): 0x00000000
Read at address 0x30101220 (0xffffb27f7220): 0x00000000
Read at address 0x30101224 (0xffffa9613224): 0x00000000
Read at address 0x30101228 (0xffffab907228): 0x00000000
Read at address 0x30101300 (0xffff925c4300): 0x00000001
Read at address 0x30101304 (0xffff80fb8304): 0x80000111
Read at address 0x30101308 (0xffffa7ffe308): 0x00010000
Read at address 0x3010130C (0xffff90ebb30c): 0x00000100
Read at address 0x30101310 (0xffff88aa1310): 0x00000000
Read at address 0x30101314 (0xffffaa3de314): 0x00000000
Read at address 0x30101318 (0xffff9da80318): 0x00000000
Read at address 0x3010131C (0xffff932bb31c): 0x00000000
Read at address 0x30101320 (0xffffb5e61320): 0x00000000
Read at address 0x30101324 (0xffff9af13324): 0x00000000
Read at address 0x30101328 (0xffffbd1f1328): 0x00000000
Read at address 0x30101400 (0xffffbb909400): 0x00000001
Read at address 0x30101404 (0xffffbdb57404): 0x80000111
Read at address 0x30101408 (0xffffb33de408): 0x00010000
Read at address 0x3010140C (0xffffbd05e40c): 0x00000100
Read at address 0x30101410 (0xffff9773b410): 0x00000000
Read at address 0x30101414 (0xffff97e71414): 0x00000000
Read at address 0x30101418 (0xffff97d3d418): 0x00000000
Read at address 0x3010141C (0xffffa0e4a41c): 0x00000000
Read at address 0x30101420 (0xffffba5a7420): 0x00000000
Read at address 0x30101424 (0xffff91fef424): 0x00000000
Read at address 0x30101428 (0xffffb99d0428): 0x00000000
Read at address 0x30101900 (0xffff987d6900): 0x00000000
Read at address 0x30101904 (0xffffa6aab904): 0x00000000
Read at address 0x30101908 (0xffff8eb05908): 0x0000007F
Read at address 0x3010190C (0xffffac3d890c): 0x00000000
Read at address 0x30101910 (0xffff7fe10910): 0x0000007F
Read at address 0x30101920 (0xffff89b71920): 0x00000000
Read at address 0x30101924 (0xffffb3852924): 0x00000000
Read at address 0x30101928 (0xffff88cee928): 0x00000000
Read at address 0x30101930 (0xffffbcbae930): 0x00000000
Read at address 0x30101934 (0xffffa3a81934): 0x00000001
Read at address 0x30101938 (0xffffbd54b938): 0x00000000
Read at address 0x30101940 (0xffff80f11940): 0x00003FFF
Read at address 0x30101944 (0xffffae0bc944): 0x00000000
Read at address 0x30101FFC (0xffffb5207ffc): 0x50220200

Table 14-19549. RX_SHIM_VBUSP_MMR_CSI2RXIF, RX_SHIM_VBUSP_MMR_CSI2RXIF Registers
base = 0x30102000
Read at address 0x30102008 (0xffffa9c63008): 0x00000000
Read at address 0x3010200C (0xffff968cc00c): 0x00000000
Read at address 0x30102010 (0xffff9f4b6010): 0x00000F01
Read at address 0x30102020 (0xffff85639020): 0x8010002C
Read at address 0x30102024 (0xffff9e789024): 0x00000000
Read at address 0x30102028 (0xffff94796028): 0x00000000

Table 14-19773. VBUS2APB_WRAP_VBUSP_K3_DPHY_RX, VBUS2APB_WRAP_VBUSP_K3_DPHY_RX Registers
base = 0x30110000
Read at address 0x30110020 (0xffffa6f49020): 0x00000429
Read at address 0x30110040 (0xffff89305040): 0x00800000
Read at address 0x3011004C (0xffffbda6604c): 0x00000000
Read at address 0x30110050 (0xffffaa36a050): 0x00000000
Read at address 0x30110B00 (0xffff9b8b7b00): 0x00000273
Read at address 0x30110B04 (0xffffb1334b04): 0x00000000
Read at address 0x30110B08 (0xffffb2062b08): 0xAAAAAAAA
Read at address 0x30110B0C (0xffffb9127b0c): 0x000000AA

0 jian wen 2 months ago in reply to Jianzhong Xu

Prodigy 130 points

Jianzhong Xu said:
Also, when your DPHY operates at 1.5Gbps lane speed, your DPHY Tx should send a deskew sequency so that the DPHY RX on the SoC is properly calibrated to receive data at 1.5Gbps.

is the 1.5Gbps different with 1G or 800M?

why do 1G and 800M work, but 1.5G does not?

0 lion chen 2 months ago in reply to Jianzhong Xu

Prodigy 30 points

Wenjian's response was for another project where SPAD is directly connected to the SoC. In this case, MIPI data can be received, but there are still some strange issues.

back to the scenario of FPGA connected to the SoC, I read back the register 0xb00, and its value is 0x273. The bit[4:0] of this register is indeed 0x13, indicating the configuration is correct. Regarding the SoC streams, currently data lanes 0-3 are mapped to streams 0-3 respectively. If only stream 0 is used,

Does it mean the maximum rate of stream 0 is 1.5G?
Is it necessary to map all data lanes to stream 0?
Will this increase the maximum rate of stream 0 to 6G?

0 Adam Hua 2 months ago in reply to lion chen

TI__Expert 4780 points

Hi Lion,

Just update info I put in email here to get others in the same page after our visit.

Data rate	TI EVM	Customer board A	Customer board B
800Mbps per lane	Success	Success	Not tested
1.2Gbps per lane	Success	Frame loss	Success
1.4Gbps per lane	Success	Frame loss	Failed
1.5Gbps per lane	Failed	Failed	Not tested

Here are a few points about this table:

Success means data is received and no frame loss is observed. Failed means no data is received and error is suggested from status register.
Customer board A and customer board B differs only at few lanes connected externally to enable measurement on board B.
For 1.5Gbps, descrew calibration is required but the register on SOC suggest no such package is correctly received.
1.4Gps per lane should be enough for customer’s use case.

Regards,

Adam

0 Jianzhong Xu 2 months ago in reply to Adam Hua

TI__Guru 58915 points

Hi Lion,

lion chen said:
Regarding the SoC streams, currently data lanes 0-3 are mapped to streams 0-3 respectively.

I do not understand what you meant here by "stream". All data lanes are used to receive the same frame transmitted from the CSI TX.

It may be helpful to send a dskew sequence from the CSI TX for those failed cases, even for <1.5Gbps.

Regards,

Jianzhong

0 Yong Zhang 2 months ago in reply to Jianzhong Xu

TI__Genius 16701 points

Dear Lion.

would you please help share the status on your side? what do you need support from TI?

thanks a lot!

yong

0 Yong Zhang 1 month ago in reply to Yong Zhang

TI__Genius 16701 points

Dear Lion.

please let us know if you still need support on this ticket. Or we can close this ticket in this week, right?

thanks a lot!

yong

0 jian wen 1 month ago in reply to Yong Zhang

Prodigy 30 points

Sorry, I am so busy these days that I have not seen this ticket.
I will test this patch on this Monday, please wait for one or two days

thanks

0 jian wen 1 month ago in reply to jian wen

Prodigy 130 points

sorry, I replied in wrong ticket

lion chen
please answer it, thanks

0 Yong Zhang 1 month ago in reply to jian wen

TI__Genius 16701 points

Dear Lion.

we will close this ticket. and please notice HW review is necessary for CSIRX as low speed only is ok.

thanks a lot!

yong

Processors

Processors forum

AM625: can not receive any data from mipi