Hello Sung-IL,
Hardware UART
The input clock to the hardware UART peripheral is 192MHz according to the AM62x clock tree tool:
So if there was an 8x oversampling mode, then 24MHz would be possible (192MHz / 8). However, the PRU hardware only allows for 16x oversampling, or 13x oversampling. Thus the hardware UART peripheral in the PRU subsystem only supports up to 12MHz baudrate.
From the AM62x Technical reference manual, PRU > PRUSS UART
7.4.7.2.4 PRUSS UART Clock Generation and Control
The PRUSS UART0 bit clock is derived from an input clock to the PRUSS UART0. See the device-specific
Datasheet to check the maximum data rate supported by the PRUSS UART0.
Figure 7-45 is a conceptual clock generation diagram for the PRUSS UART0. The processor clock generator
receives a signal from an external clock source and produces a PRUSS UART0 input clock with a programmed
frequency. The PRUSS UART0 contains a programmable baud generator that takes an input clock and divides
it by a divisor in the range between 1 and (216 - 1) to produce a baud clock (BCLK). The frequency of BCLK is
sixteen times (16×) the baud rate (each received or transmitted bit lasts 16 BCLK cycles) or thirteen times (13×)
the baud rate (each received or transmitted bit lasts 13 BCLK cycles). When the PRUSS UART0 is receiving,
the bit is sampled in the 8th BCLK cycle for 16× over sampling mode and on the 6th BCLK cycle for 13×
over-sampling mode. The 16× or 13× reference clock is selected by configuring the mode definition register:
UART_MODE[0] OSM_SEL bit. The formula to calculate the divisor is:
Divisor = UART input clock frequency [MODE.OSM_SEL = 0h]
-------------------------------------
Desired baud rate x 16
Divisor = UART input clock frequency [MODE.OSM_SEL = 1h]
-------------------------------------
Desired baud rate x 13
