Tool/software:
Dear TI Support Team,
I am working on a custom AM335x-based embedded board designed for real-time Ethernet communication. The board is equipped with the DP83867ERGZ Ethernet PHY, and our goal is to achieve Ethernet latency of less than 1 millisecond at 100 Mbps full-duplex communication.
We are using the TI Processor SDK v05.00.00.15 with Linux Kernel 4.14.40. Given the critical nature of our application, we are seeking your expert guidance on:
1. Steps to Achieve <1ms Ethernet Latency
Could you please provide detailed recommendations or steps we can follow to meet our latency target?
Specifically, we are looking for advice in the following areas:
a. PHY-Level Optimizations (DP83867ERGZ):
Are there any PHY register settings or strap configurations that help in reducing transmit/receive delays?
Is there a way to disable deep FIFO buffering or reduce internal latency in the PHY?
Should we enable RGMII RX/TX delay or configure specific clock skews?
b. is there we need to change in the driver code or is there we need to change in the kernel
2. Ethernet Latency and Speed Testing Procedure
We would also like to understand the recommended testing methodology for validating Ethernet latency and throughput on the AM335x platform. Specifically:
What TI-recommended tools or utilities are available to test latency between two boards?
Can you provide a procedure using tool like ping in a real-time context?
What is the expected baseline latency of the AM335x CPSW + DP83867 PHY at 100 Mbps in an optimized setup?
3. Additional Guidance Requested
Are there any existing application notes, reference designs, or technical whitepapers from TI that cover real-time or low-latency Ethernet configurations on the AM335x platform?
Any support or direction you can provide will be highly appreciated, as meeting this latency goal is critical to the success of our project.
Thank you in advance for your time and support. I look forward to your expert recommendations and references.
